FPGA breakthrough paper in the January issue of Nanotechnology: "Nano/CMOS architectures using a field-programmable nanowire interconnect," by Gregory Snider and Stanley Williams of HP Labs.
"Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 × to 25 ×), reduced power, slightly lower clock speeds, and high defect tolerance..." 25 times, whew!
The paper is available free for the next month or so on the IOP website,
Nano Crossbar switch interconnect on top of mostly standard CMOS.
They mentioned the likelihood of high defect densities with the nano parts in the review I saw.
Robert
And discussed in the paper. Greatly reducing the transistor sizes leads to high defect rates, but the interconnects allow them to wire around the defects and use the chip at its full capability, even with up to 25% defect rate, IIRC. The full paper is worth reading.
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