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PLL Loop filter

This PLL loop filter is used with current-output charge-pumps:

GND === .---. | .-| Z |-. --- | '---' | --- | | i_N | ___ | |\ | -->----o---|___|--o--|-\ | ___ | >-o--- -->----o---|___|--o--|+/ i_P | | |/ --- ,---. --- | Z | | '---' === | GND === GND

Z is an R and C in series, optionally paralleled with another C.

This circuit can be used with voltage-output phase detectors; but the single-ended input impedances are not equal:

GND === .---. | .-| Z |-. --- | '---' | --- | | ___ | ___ | |\ | VN --|___|---o---|___|--o--|-\ | ___ ___ | >-o-- VP --|___|---o---|___|--o--|+/ | | |/ --- ,---. --- | Z | | '---' === | GND === GND

This circuit seems to have better input balance over a wider frequency range and is simpler:

GND === .---. | .-| Z |-. --- | '---' | --- | | ___ | ___ | |\ | --|___|---o---|___|--o--|-\ | ___ ___ | >-o-- --|___|---o---|___|--o--|+/ | |+ |/ --- --- --- === 10uF | | === === GND GND

Is there a downside?

TIA

Reply to
Andrew Holme
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A few more details for clarity: I'm using an AD9901-style PFD inside an FPGA which feeds this circuit differentially, via LVDS out of the FPGA and is then level shifted to CML to get the common mode voltage up enough that I don't need a negative supply for the op-amp.

Reply to
Andrew Holme

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