efficient low-voltage boost converters

On Tuesday, August 30, 2016 at 9:42:44 PM UTC-4, snipped-for-privacy@yahoo.com wrote :

your favorite high efficiency low power boost controller IC without it goi ng into PFM or burst mode of some kind at low duty cycle:

on.

Steady state duty D is computed by balancing the net magnetizing flux excur sion per cycle to zero by averaging the impressed voltage per cycle to zero . Assuming the magnetizing inductance to be in parallel with the winding in series with switch to GND, the N turn winding, the ON state average voltag e is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum those to 0 a nd you should get the result shown on the schematic. Rather than working th e calculus on that expression, it is simpler to tabulate D at the extremes of input voltage as a function of winding ratio N. For N=3 the duty runs from 20-35% which is a bit more tame.

On Tuesday, August 30, 2016 at 9:42:44 PM UTC-4, snipped-for-privacy@yahoo.com wrote :

your favorite high efficiency low power boost controller IC without it goi ng into PFM or burst mode of some kind at low duty cycle:

on.

The whole purpose of the step-up from secondary to primary is to speed the discharge. And the voltage drop across the diode, which I've neglected for purposes of preliminary estimation of circuit function, actually helps with that. I'm pretty sure this is more properly termed a flyback, and it does stack that boosted differential on top of the input voltage.

No, it's the opposite. Coupled inductors are used to lengthen the discharge, creating a more manageable duty cycle -- otherwise it's hard to keep a high- ratio boost converter's inductor in continuous mode, when the discharge time approaches 'instantaneous.'

Using coupled inductors has the added benefit of reducing peak currents & i^2r losses.

True, but that's an unhelpful loss. I was ignoring it for this discussion, though.

Yes, it's a flyback, a boost converter with a coupled inductor.

Cheers, James Arthur

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th your favorite high efficiency low power boost controller IC without it g oing into PFM or burst mode of some kind at low duty cycle:

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ursion per cycle to zero by averaging the impressed voltage per cycle to ze ro.

Yes.

series with switch to GND, the N turn winding, the ON state average voltag e is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum those to 0 a nd you should get the result shown on the schematic. Rather than working th e calculus on that expression, it is simpler to tabulate D at the extremes of input voltage as a function of winding ratio N. For N=3 the duty runs from 20-35% which is a bit more tame.

I find a simple sanity-check helpful: if you charge a given inductor with a given voltage, it'll take ten times longer to discharge at one-tenth that voltage.

In this case (2.2V charging, and 0.2V across each inductor, discharging) th e ratio is eleven, so I predict a continuous-mode duty-cycle of 1/12th.

This is nothing more than calculating the ripple current, di = dt*E/L, an d realizing that it has to balance going up, and going down.

It works. Try it. (I set the load voltage low to compensate the diode drop .)

Version 4 SHEET 1 880 680 WIRE 192 80 32 80 WIRE 320 80 256 80 WIRE 432 80 384 80 WIRE 192 96 192 80 WIRE 256 96 256 80 WIRE 32 128 32 80 WIRE 432 128 432 80 WIRE 192 208 192 176 WIRE 256 208 256 176 WIRE 256 208 192 208 WIRE 32 224 32 208 WIRE 432 240 432 208 WIRE 192 272 192 208 WIRE 144 352 -48 352 WIRE -48 368 -48 352 WIRE 192 400 192 368 WIRE -48 464 -48 448 FLAG 32 224 0 FLAG 192 400 0 FLAG 432 240 0 FLAG -48 464 0 SYMBOL ind2 176 80 R0 WINDOW 0 -46 34 Left 2 WINDOW 3 -65 75 Left 2 SYMATTR InstName L1

SYMATTR Type ind SYMBOL ind2 272 192 R180 WINDOW 0 -36 57 Left 2 WINDOW 3 -58 22 Left 2 SYMATTR InstName L2

SYMATTR Type ind SYMBOL schottky 320 96 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N5819 SYMATTR Description Diode SYMATTR Type diode SYMBOL voltage 32 112 R0 SYMATTR InstName V1 SYMATTR Value 2.2 SYMBOL nmos 144 272 R0 SYMATTR InstName M1 SYMATTR Value AP9465GEM SYMBOL voltage 432 112 R0 SYMATTR InstName V2 SYMATTR Value 2.4 SYMBOL voltage -48 352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(0 10 0 30n 30n 1u 20u) TEXT 184 16 Left 2 !K1 L1 L2 1 TEXT -82 488 Left 2 !.tran 100u

Cheers, James Arthur

On Wednesday, August 31, 2016 at 10:55:18 AM UTC-4, snipped-for-privacy@yahoo.com wr ote:

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with your favorite high efficiency low power boost controller IC without it going into PFM or burst mode of some kind at low duty cycle:

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xcursion per cycle to zero by averaging the impressed voltage per cycle to zero.

in series with switch to GND, the N turn winding, the ON state average volt age is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum those to 0 and you should get the result shown on the schematic. Rather than working the calculus on that expression, it is simpler to tabulate D at the extreme s of input voltage as a function of winding ratio N. For N=3 the duty run s from 20-35% which is a bit more tame.

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That's not the circuit I drew. I'm not going to argue fundamentals with you , go back and review, then run the circuit I actually drew and try to figur e it out. Anything in disagreement with my claims is wrong.

Hmm, I just noticed that the two centre-taps are connected together, so I guess they could be an auto-transformer, to save a bit more on the copper losses and leakage inductance. Due to the high ratio of primary to secondary turns that might not help much - not many of the primary turns would be shared.

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excursion per cycle to zero by averaging the impressed voltage per cycle t o zero.

g in series with switch to GND, the N turn winding, the ON state average vo ltage is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum those to 0 and you should get the result shown on the schematic. Rather than workin g the calculus on that expression, it is simpler to tabulate D at the extre mes of input voltage as a function of winding ratio N. For N=3 the duty r uns from 20-35% which is a bit more tame.

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ou, go back and review, then run the circuit I actually drew and try to fig ure it out. Anything in disagreement with my claims is wrong.

We're not differing on fundamentals, I just 'auto-corrected' your circuit t o what I thought you meant, once I thought I'd recognized it as attempting a conventional coupled-inductor boost.

Here's your circuit repeated, slightly reformatted: Vx D1 . Vin>--------+------. .----|>|---+----> Vout . | | | | . o ) || ( o | | . ) || ( | --- C1 . L1 ) || ( L2 | --- . ) || ( | | . ) || ( | | . | | | | . |Vsw '-----' | . | | . switch | . Boost Conv IC | . | | . --- ----

If I've drawn that correctly, I don't understand the point. Vx=Vsw, so L2 seems moot. Might as well tie D1 to Vsw and eliminate L2, a standard boost.

Cheers, James Arthur

Sounds right on all points.

As a practical matter ISTM Win's looking at a micro-power boost topology with a synchronous switch for a rectifier. Otherwise, even a schottky diode loses him 10% (or more).

Cheers, James Arthur

On Wednesday, August 31, 2016 at 12:16:59 PM UTC-4, snipped-for-privacy@yahoo.com wr ote:

ive with your favorite high efficiency low power boost controller IC withou t it going into PFM or burst mode of some kind at low duty cycle:

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ux excursion per cycle to zero by averaging the impressed voltage per cycle to zero.

ing in series with switch to GND, the N turn winding, the ON state average voltage is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum those to 0 and you should get the result shown on the schematic. Rather than work ing the calculus on that expression, it is simpler to tabulate D at the ext remes of input voltage as a function of winding ratio N. For N=3 the duty runs from 20-35% which is a bit more tame.

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you, go back and review, then run the circuit I actually drew and try to f igure it out. Anything in disagreement with my claims is wrong.

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Okay- you're halfway there, now run the simulation and check out the duty c ycle. The secondary reverse biases the diode when SW is on, so it's out of the circuit at that point. During flyback when the SW is off, the stored ma gnetic energy discharges through the secondary into the load. Vin and Vout clamp and set the secondary voltage which is stepped-up across the core exp ressly to speed the discharge time so the duty cycle has to settle at a mor e reasonable value in the 20-40% range thus enabling the use of more conven tional off the shelf boost controller PWM with internal reference. Last tim e I checked even the high frequency ferrite power dissipation goes as Freq^

3, so for high efficiency the MHz operation probably is not competitive wit h more reasonable circuits in the 20-100kHz range at 0.001 the core loss, a nd winding resistance is a non-issue at the currents we're talking about he re.

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flux excursion per cycle to zero by averaging the impressed voltage per cyc le to zero.

nding in series with switch to GND, the N turn winding, the ON state averag e voltage is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum thos e to 0 and you should get the result shown on the schematic. Rather than wo rking the calculus on that expression, it is simpler to tabulate D at the e xtremes of input voltage as a function of winding ratio N. For N=3 the du ty runs from 20-35% which is a bit more tame.

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th you, go back and review, then run the circuit I actually drew and try to figure it out. Anything in disagreement with my claims is wrong.

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cycle. The secondary reverse biases the diode when SW is on, so it's out o f the circuit at that point. During flyback when the SW is off, the stored magnetic energy discharges through the secondary into the load.

I agree with all that, but since L1=L2, you're just charging one inductor then discharging its stored energy through a 2nd set of windings, of the same inductance value, connected through a common magnetic circuit.

The result is no different than a simple boost--you can get the same D1 current by deleting L2 and tying Vx to Vsw.

Cheers, James Arthur

ss the core expressly to speed the discharge time so the duty cycle has to settle at a more reasonable value in the 20-40% range thus enabling the use of more conventional off the shelf boost controller PWM with internal refe rence. Last time I checked even the high frequency ferrite power dissipatio n goes as Freq^3, so for high efficiency the MHz operation probably is not competitive with more reasonable circuits in the 20-100kHz range at 0.001 t he core loss, and winding resistance is a non-issue at the currents we're t alking about here.

Sometimes efficiency is everything. My roof has 34 solar panels, one sun rated at 280 watts. If they were 10% better, 308 watts, I could have installed 31 panels, and saved $2,800. My low-voltage-boost project is similar. It's for a lab demonstration with a one-sun source and a triple-junction solar cell driving an electrochemical production cell.

The triple-junction solar cell generates about 2.4V at MPP, and the electrochemical cell wants 2.6V for an optimized product output. At lower voltages it generates mostly hydrogen. The two work when hooked together, but product output is more than 10% degraded. A 2.4 to 2.6V boost converter could save the lost 10 to 15%, but if it consumes 10 to 15% in the process, then it has lost the job assignment.

Of course, this is just a lab demonstration, a kind of small competition actually. One rarely gets full sunlight in the real world, and an efficient boost converter, plus other features, would be required. Working at higher power levels, it likely wouldn't be a particularly difficult task.

--
 Thanks, 
    - Win

On Wednesday, August 31, 2016 at 1:15:55 PM UTC-4, snipped-for-privacy@yahoo.com wro te:

n drive with your favorite high efficiency low power boost controller IC wi thout it going into PFM or burst mode of some kind at low duty cycle:

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g flux excursion per cycle to zero by averaging the impressed voltage per c ycle to zero.

winding in series with switch to GND, the N turn winding, the ON state aver age voltage is D x Vin, and the OFF state is (1-D) x N x (Vin-Vout). Sum th ose to 0 and you should get the result shown on the schematic. Rather than working the calculus on that expression, it is simpler to tabulate D at the extremes of input voltage as a function of winding ratio N. For N=3 the duty runs from 20-35% which is a bit more tame.

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with you, go back and review, then run the circuit I actually drew and try to figure it out. Anything in disagreement with my claims is wrong.

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ty cycle. The secondary reverse biases the diode when SW is on, so it's out of the circuit at that point. During flyback when the SW is off, the store d magnetic energy discharges through the secondary into the load.

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What is it about N:1 you don't understand, how could L1 possibly equal L2? In the case N=1, it degenerates into nonsense.

ross the core expressly to speed the discharge time so the duty cycle has t o settle at a more reasonable value in the 20-40% range thus enabling the u se of more conventional off the shelf boost controller PWM with internal re ference. Last time I checked even the high frequency ferrite power dissipat ion goes as Freq^3, so for high efficiency the MHz operation probably is no t competitive with more reasonable circuits in the 20-100kHz range at 0.001 the core loss, and winding resistance is a non-issue at the currents we're talking about here.

25-30 years ago I built thousands similar using an HC132 to create 5V from 2.2-3V at 1mA max load but I was never bothered too much about efficiency. Small size, low cost and low parts counts were my drivers. I do remember that I had to use the highest value inductors - 1mH was the biggest I could get SMD back then within my height restriction.

Lower Rds-on chips paralleled together and optimized inductor choices might get your target efficiency.

I thought I was pretty nifty using a logic gate as a synchronous rectifier back before they were mainstream!

piglet

Indeed you were!

--
 Thanks, 
    - Win

Betting I could cook up a "Joule Thief" that gets there. Is a MMBT2222W too big and expensive for you? ;-)*

*Wink for the implicit dual winding inductor. Which really isn't so bad, what with such things existing these days. But a sufficiently small and cheap one, also with enough inductance (~1mH for this current?) seems unlikely.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

Sure, when you just spent $100K on the panels, it's makes sense to spend $2 on an inductor. Engineering is economics.

Engineering is also about understanding the whole problem. ;-)

It's all just money.

Sure they exist: Common mode chokes. Many can tolerate a few milliamps before the core saturates. I have used them in unorthodox ways.

--
Regards, Joerg 

http://www.analogconsultants.com/

Hmm, it'll be rather large. (Should come in under a buck, though!)

I wonder if some SMT chokes use unconventional materials or core designs (i.e., something with a little accidental gap, or low mu), that can handle more magnetization.

You'd have to buy up so many and inspect and test them...

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com

Check out the telco versions which reside in modems and such. Also for data communications gear.

It needs to be clearly spec'd.

That would become an eternal white-knuckle ride and can fly in your face if the mfg changes process.

--
Regards, Joerg 

http://www.analogconsultants.com/