Bar>Point proved !
True. You're as ignorant as you were before. Try to put words in my mouth that I didn't say and I'm coming after you, s*****ad.
...and John S is another one who makes it up as he goes along.
John Devereux Inscribed thus:
I understood that.
Part of this seems very odd for a product that, despite various limitations can be obtained and used for free ! I see that the file format can be taken and converted for other applications. So I'm more inclined to belive that there were other factors involved.
Thanks.
--
Best Regards:
Baron.
into
It's a netlist transport format. If all you want is to move a netlist, EDIF is the way to go. Chip makers use it as you would a Gerber.
Maybe that was your wish. No one else had that fantasy, though. ;-)
...and that's its most enduring feature. ;-)
Not just software. "Buy it to bury it." ...except they can't even do that right. I'm learning Zuken, these days. What an absolute nightmare, compared to OrCAD. The Germans are *nutz*. Well, at least it doesn't crash, much.
into
advantage
There we use GDS-II, probably goes all the way back to the days I wore diapers.
A common format just for netlisting isn't very useful, I never felt the urge for a standard there. Typically I spool out a PADS netlist and that can be read in by almost any layout software.
That goal was all over the trade publications back then. I never believed it would come to fruition though, and it didn't.
I still remember a support call where finally someone on their side exclaimed "I can't believe this is happening!".
I thought that's a Japanese CAD system. German software is usually pretty good, like Eagle which never crashes. The marketing side over there is often rather weird though. I will never understand why Cadsoft isn't going more after corporate users where they could sell dozens of licenses in one fell swoop. Without a hierarchy they are leaving tons of money on the table.
-- Regards, Joerg http://www.analogconsultants.com/
into
advantage
Tell chip makers that! EDIF *was* our product. FPGA software uses EDIF, as well.
You gotta stop reading that crap.
trade magazines ~= New York Times
No intelligence there.
I could make 16.1 crash at will. Simply select good chunk of a page, and drag. Sometimes one component was enough but half a page would do it every time. 16.3 *mostly* fixed that. Perhaps they didn't want the problem so easily reproduced.
I hadn't actually looked. It's starting to make a *whole* lot more sense (the Japanese are ;).
Hierarchy? I'd be happy to be able to print more than one page at a time. :-(
Whoa! Make up wot? I've seen your complaints now for years. Same old story. I never said that you were lying. I believe your story.
Now, show me where I made something up about you, Mr. Useless Scum Bag.
guys
designs into
advantage
Then why do ours always use GDS-II? FPGA stuff is usually highly proprietary to the respective product line, I wouldn't know what would be exchangeable or standardized there. The only thing you have is conversion services, in case your volume goes up and you want it all poured into an ASIC.
The whole sob story is summed up here and the word that, not surprisingly, darts out is "problem":
Quote "The vendor companies did not always feel it important to allocate many resources to EDIF products, even if they sold a large number of them. There were several stories of active products with virtually no-one to maintain them for years. User complaints were merely gathered and prioritized. The harder it became to export customer data to EDIF, the more the vendors seemed to like it".
You don't ever read EETimes, EDN and stuff? I don't spend a lot of time there but occasionally it nets me a hint to a product I might otherwise have missed because it was geared towards a very different market.
I crashed it several times a day using integrated PSpice.
Ugh. That sounds bad. That software goes on my "not to do" list :-)
-- Regards, Joerg http://www.analogconsultants.com/
John S wrote:
Reading comprehension problems, then? Lousy memory? Never actually clicked the link I always post?
Right. Instead, you made up your own narrative and claimed it is mine.
You'd have to KNOW it first.
news:jd0pjc$sq9$ snipped-for-privacy@dont-email.me
Cadsoft never got the opportunity to abuse me with their DRM. I am, however, VERY angry that I had previously been responsible for the scumbags getting some money from my previous company.
Surreptitious bombs purposely put into software by its vendor just makes me see red. When that is in a tool that could blow up in your face when you're on deadline, the steam comes out my ears. When the company then tells you "Go f*ck yourself, Mr. Paid-Up customer", that's the limit. Anyone who endorses that kind of corporate behavior would also sell out to any slimeball who is the highest bidder.
stuff.
Wow. That would take a massive malfunction in the architecture to prevent developing code for hierarchal schematics and layouts. Hell they go hand in hand.
?-)
If you set it up correctly, the Eagle Autorouter works very well. I used it to autoroute high-current (20 amps or so) and low current (mA) on the same board with no problems. Please note that you can route traces individually.
No worse than yours.
Yes, I did, more than once. More than enough.
Made up? Post my made-up narrative.
I only read your link a few times. Is that knowing?
In what way was it fabricated? Show me.
None of this is your fault, of course. The fact that you used some unknown piece of an (illegal, according to Eagle) Eagle layout for your own purpose is not your fault.
Of course. That's your vendetta. Have you learned to stay away from the bombs? It seems that yours is the only complaint. Do you have links to others who have complained similarly?
Of course. That's your vendetta.
Of course. That's your vendetta.
I don't endorse it. You have, in my opinion, a legitimate complaint. Most of us are just sick of you jumping in and ranting on every post that has Eagle or Cadsoft. We already know about you and your hate thing. Give it a rest.
Yet even Cadence couldn't get it to work in OrCAD until last year. Allegro doesn't really use hierarchy either.
guys
believe
is
Designing,
designs into
advantage
lowest
Different animals completely. GDS ~= Gerber. EDIF is a netlist standard.
Within the tools the netlists are in EDIF. EDIF is used for third-party tools, as well.
You're talking about different "vendors" than I'm familiar with, at least at that end of the business. Of course, EDIF isn't important for board level tools.
Nope, not for at least thirty years. They're a complete waste of time.
compared
As I mentioned, I'm just learning the tool (a couple of weeks in on a hot design) so there may be things I'm missing but so far no one has been able to show me how to print multiple pages. They tell me that to print PDFs, they do one page at a time and then use Acrobat to stitch them together. Yeah, major ugh! It does look like the tool supports hierarchy, though. No one uses hierarchy or, I think, knows what to do with it, so I'll have to play with it.
So, then, which vendors are we talking about? Last time a move between a Mentor system to a Cadence system was contemplated the talk turned towards the effort of file conversion (schematic level, for a large IC). This effort was considered major. So far for EDIF ...
I don't read them often but glance over them. Many times I found gems, cases where one of my clients had an almost perfect "wacky use" for some IC. Their EEs missed it because they didn't keep an eye on these magazines.
In fact, sometimes they pay me for keeping that eye open :-)
[...]
:-(
That's because you aren't working in a heavily regulated industry, else your colleagues would be familiar with it. I doubt anyone would dare to submit a set of schematics for a very large system in med or aero without a properly organized hierarchy. It would be like telling the tax auditor "Here, it's all in this Hefty bag, somewhere".
-- Regards, Joerg http://www.analogconsultants.com/
Chip manufacturers.
As I said above, EDIF's function is not to draw pretty pictures, rather take the netlist generated by the schematic capture to the next level. I don't recall even any reverse annotation.
A cow-orker used to send an article around once in a while with some comment that we could use some technique or other. In every case it was something incredibly obvious, that everyone in this group (less DimBulb and Slowman) has been doing for decades, that the author was trying to claim as his own.
As I said, a total waste of time.
:-(
Could easily be. I rather like hierarchical designs. If for no other reason, it makes schematics far easier to read. Recently someone (here?) was arguing that there was no need. I asked if he wrote flat VHDL, too.
They just get the GDS-II files and make our wafers. Or did you mean TI, AD, ON Semi and so on? Can't imagine that they dont' use the major CAD suites. The schematic file formats between those suites of different vendors are incompatible from what I've been told many times.
That is a far cry from what EDIF was touted to be. In German they have a saying which loosely translates into "The mountain has reached full term, and it gave birth to a mouse" :-)
Not all all to me. Has about the same value as some select (very few) manufacturer email updates. Takes 1-2 min to read through diagonally. If this nets 1-2 wacky uses for an off-market chip per year, and it usually does, then the ROI is huge. I've had cases where the cost of a module dropped by a couple hundred bucks because a consumer chip could replace a super expensive boutique set of parts.
Depends on the field you are working in though. For RF there ain't too much use in this. For ultrasound, laser stuff, fast machine control, very different story.
:-(
do
it.
Take a look at his tool cabinets. They are probably a royal mess :-)
-- Regards, Joerg http://www.analogconsultants.com/
I mean TSMC, IBM, and such. Again, schematics output netlists, which like Humpty, can't be put back together into pretty picture schematics.
Touted by your "industry newsletters"? That's what it *is*.
I read very few of the manufacturer's emails. When I need something I search their web sites.
time. :-(
to
do
major
it.
Ulp! I resemble that. ;-)
at
So are they not using Mentor and Cadence?
No, touted by all sorts of bigshot EDA companies.
has
That is exactly why I am sometimes the first to come up with a "wacky use" idea for a part. Because of the "when I need something" effect. By then engineers are typically already under schedule pressure and, guess what, they immediately scoot over to Analog Devices or LTC. There they find the $3.50 part that does the job. It's good stuff, support is great and they know it'll work.
Then comes yours truly, proposing to use this automotive IC instead because it's only 31 cents a piece, and some jaws drop. Usually the only reason I come up with ideas like that is because I've read about it a few months ago, can't quite remember where, but remember enough bits and pieces about it that a few minutes on the web will find it back. Without reading industry newsletters this would usually not happen.
All this probably means little to you because your company doesn't design real mass products, stuff where 5k units/mo roll off a conveyor belt in Guangdong. Then such a price difference matters, big time.
time. :-(
to
they do
major
it.
reason,
My wife sez me too :-(
Fixing her sewing machine right now.
-- Regards, Joerg http://www.analogconsultants.com/
[...]
Sorry, meant EDA distributors.
[...]-- Regards, Joerg http://www.analogconsultants.com/
It diffused northward when Rome fell. ;) That's a quotation from one of Horace's odes: "Parturient montes, nascetur ridiculus mus". See e.g.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.