Do I need some sort of delay between two latch circuits?

The textbook should have all of the information you need to solve this, albeit you might have to crib someone else's lecture notes.

Failing that, you could slap one together on a piece of perfboard, get a scope, and see what happens.

Good Luck! Rich

"laylow" schreef in bericht news: snipped-for-privacy@w3g2000hsg.googlegroups.com...

You have to specify what sort of logic you are using, and what supply voltage.

The information you need is buried in the data sheets for the devices that you are actually using - the data sheets specify the range of propagation delays you are likely to see, and the set-up times and hold times that you will have to conform to if you want to be sure that the latches behave as intended.

Even the fastest logic commercially available - ECLinPS - has propagation delays, set-up times and hold times that aren't much less than a nanosecond, which is about 20cm (eight inches) of propagation delay along a typical printed circuit board, so using a longer trace is unlikely to be a practical solution.

Resistor/capacitor lumped delays can work, but the large tolerances on the logic threshold levels can make for very large tolerances (up to 10:1 in some pathological cases) in the delay that you actually get.

I've used lumped constant delay lines, but this tends to be a bulky and expensive solution. In clocked systems, you usually organise things so that successive events happen on successive clock edges.

--
Bill Sloman, Nijmegen

Yes, a simple 1 Meg resistor feeding a 10 Farad capacitor will certainly delay the signal enough if you are using any of the CMOS technologies.

Unfortunately, I don't have a text book. I meant to get one once but never did. I'm an amateur and by the time I get around to asking a question in a group my brain is fairly mushy.

I was planning to use 74HC chips which I believe are CMOS circuits. Are the 7400's TTL? Any reason why I might want to use the 7400's instead of the 74HC's? The latches would be made by crossing the outputs of two NOR gates with their inputs. The supply voltage is

5VDC.

It's good to know that the data I need should be buried in the data sheets. I just hope that I can find it, recognize it, and understand it.

So I guess I can look up the 74HC02's and hope that resetting is faster than setting. If that fails, I can wait for my parts to come in and see if the resistor/capacitor delay works for me. And if that doesn't work then I guess it's time to learn about clocked systems.

Well, I'll read everything I can but believe me, I don't mind being spoon-fed either.

Thanks Group! Laylow

Sorry for being so redundant but I think I have a better idea of what my question is now. Looking at the data sheet I can see that the propagation delay for each gate is around 23ns. Resetting a latch only requires the signal to pass through one gate while setting the other latch requires the signal to pass through two gates. So I think that means both latches will output low for about 23ns before the second latch goes high. Is that enough to reliably prevent the AND gate from going high? It's the reliable part that I'm concerned about.

Thanks again, Laylow

If you've seen one textbook, you've seen them all.

There's rumored to be a CMOS cookbook out there somewhere.

-- Many thanks,

Don Lancaster voice phone: (928)428-4073 Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552 rss:

email: snipped-for-privacy@tinaja.com

Please visit my GURU's LAIR web site at

Howcome HCMOS is limited to +4.95V < Vcc < +5.05V? Has anybody toyed with the idea of CMOS that has robust outputs but can run from a higher Vcc? Or is the thrust these days to lower and lower Vcc's?

Thanks, Rich

--
Probably not.  As others have suggested, consult the data sheets for
propagation delays, setup and hold times, etc.

Your description is too vague. If you can get more specific about the transducers firing in order, and what they're firing, then we might be able to suggest a "hazard free" implementation.

It isn't limited like you suggest. It works from about 3V to about 6V

To make a higher voltage part, the geometries have to get larger and the on resistance of the FETs will increase. For a given cross section, the on resistance runs as something like the square of the breakdown voltage so going for a 3 times higher breakdown makes a 9 times increase in Rds(on).

If you make the cross section greater to lower the resistance, the capacitances all increase.

I still want a PIC that can withstand some 35V however.

Yes, that's it exactly. Thank you. I'm not exactly sure how to tell how much delay is needed from the data sheets but it looks like I can just pick a high enough RC time constant to be safe. I'm hoping that when I get my AOE text and work book that I'll be more comfortable with some of the more commonly used formulas. So far I have been learning everything from sites like

and

LL

Sorry. I am using two hall effect transducers to sense a magnet that is mounted on a non-ferrous disc. It is important that the disc only rotate in one direction. If the disc rotation reverses then an alarm indicator needs to light up. The hall effect transducers pass a +5VDC signal when the magnet passes them. If the disc itself were ferrous I could just use a different kind of sensor entirely.

Thanks, LL

Okay, now we know what you're trying to do. Run a search on "quadrature rotary encoder" and see if that doesn't do much better...

--
The circuit I posted for you won\'t work for that application. 

I have a simple circuit that will, but how fast is the disc rotating
and how far apart are the sensors?

Why wouldn't it work? It seems simple enough. Anyway, the disc is

14' in diameter and rotates anywhere from 1/10th to 30 RPM. A strong magnet is mounted on the outside edge of the disc. The sensors can be mounted as far apart as needed but I prefer that they be as close as possible.

LL

--
Too simple to do the job. :-(

On Sun, 22 Jul 2007 13:08:53 -0500, John Fields wrote:

--- Oops...

Don't let those CMOS inputs float when the diodes cut off!

Version 4 SHEET 1 2244 800 WIRE 352 -272 128 -272 WIRE 1104 -272 880 -272 WIRE 352 -224 352 -272 WIRE 1104 -224 1104 -272 WIRE 800 -208 480 -208 WIRE 976 -208 800 -208 WIRE 272 -176 -96 -176 WIRE 592 -176 432 -176 WIRE 976 -176 976 -208 WIRE 1024 -176 976 -176 WIRE 1248 -176 1184 -176 WIRE 272 -128 48 -128 WIRE 480 -128 480 -208 WIRE 480 -128 448 -128 WIRE 592 -128 592 -176 WIRE 800 -128 800 -208 WIRE 1024 -128 976 -128 WIRE 1248 -48 1248 -176 WIRE 240 -16 208 -16 WIRE 336 -16 304 -16 WIRE 352 -16 352 -80 WIRE 352 -16 336 -16 WIRE 384 -16 352 -16 WIRE 592 -16 592 -48 WIRE 592 -16 448 -16 WIRE 208 32 208 -16 WIRE 1104 32 1104 -80 WIRE 1104 32 208 32 WIRE 592 64 592 -16 WIRE 688 64 592 64 WIRE -96 80 -96 -176 WIRE 48 80 48 -128 WIRE 208 80 208 32 WIRE 336 80 336 -16 WIRE 480 80 480 -128 WIRE 688 80 688 64 WIRE 976 80 976 -128 WIRE 592 96 592 64 WIRE 800 128 800 -48 WIRE 800 128 752 128 WIRE -96 208 -96 160 WIRE 48 208 48 160 WIRE 48 208 -96 208 WIRE 128 208 128 -272 WIRE 128 208 48 208 WIRE 208 208 208 160 WIRE 208 208 128 208 WIRE 336 208 336 160 WIRE 336 208 208 208 WIRE 480 208 480 160 WIRE 480 208 336 208 WIRE 592 208 592 160 WIRE 592 208 480 208 WIRE 688 208 688 176 WIRE 688 208 592 208 WIRE 880 208 880 -272 WIRE 880 208 688 208 WIRE 976 208 976 160 WIRE 976 208 880 208 WIRE 1248 208 1248 32 WIRE 1248 208 976 208 WIRE -96 288 -96 208 FLAG -96 288 0 SYMBOL voltage 48 64 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 5 1 1E-6 1e-6 .1 2) SYMATTR InstName V2 SYMBOL voltage -96 64 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value 5 SYMATTR InstName V1 SYMBOL res 576 -144 R0 WINDOW 0 -37 37 Left 0 WINDOW 3 -47 72 Left 0 SYMATTR InstName R1 SYMATTR Value 1e6 SYMBOL cap 576 96 R0 WINDOW 0 -37 33 Left 0 WINDOW 3 -48 63 Left 0 SYMATTR InstName C1 SYMATTR Value 1e-6 SYMBOL Digital\\\\dflop 352 -224 R0 WINDOW 0 28 -55 Left 0 SYMATTR InstName A1 SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v SYMBOL res 464 64 R0 WINDOW 0 -32 35 Left 0 WINDOW 3 -42 68 Left 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL Digital\\\\dflop 1104 -224 R0 WINDOW 0 30 -58 Left 0 SYMATTR InstName A2 SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v SYMBOL diode 448 -32 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL diode 240 0 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL voltage 208 64 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 5 0 1E-6 1e-6 .1) SYMATTR InstName V3 SYMBOL voltage 976 64 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 5 2 1E-6 1e-6 .1 2) SYMATTR InstName V4 SYMBOL res 1232 -64 R0 SYMATTR InstName R3 SYMATTR Value 10k SYMBOL npn 752 80 M0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL res 784 -144 R0 WINDOW 0 -41 45 Left 0 WINDOW 3 -50 74 Left 0 SYMATTR InstName R4 SYMATTR Value 10K SYMBOL res 320 64 R0 WINDOW 0 41 39 Left 0 WINDOW 3 34 73 Left 0 SYMATTR InstName R5 SYMATTR Value 10e6 TEXT -72 232 Left 0 !.tran 5 TEXT -80 264 Left 0 !.option noopiter TEXT 216 168 Left 0 ;RESET TEXT 64 168 Left 0 ;FWD TEXT 984 168 Left 0 ;REV TEXT 360 -248 Left 0 ;HC4013 TEXT 1112 -248 Left 0 ;HC4013

-- JF

Well, that looks like it will work. I don't know if I ever would have been able to come up with it. This is a circuit that you already had? What was it for? I still wish I knew what was wrong with the other circuit. I suppose I wouldn't find out without breadboarding it first.

So just to be sure I have things straight, V1 is the 5V supply, V2 simulates the first hall sensor, V3 is a manual push button reset, and V4 is the second hall sensor. The pulse from V2 causes A1Q to go hi which starts to charge C1. I'm not sure what happens next with C1. I suppose it just slows the signal that will clear A1. When A1 clears then A1Q| goes hi so that A2Q will go hi when V4 sends its signal. I guess it also shorts C1 to ensure that A1 doesn't somehow clear (I never would have guessed that that was something that needed to be done). Anyway, A2Q goes hi and then from what I can tell it stays hi. The next time A1 receives a pulse both A1Q and A2Q will be hi at the same time giving me an error. I suppose the circuitry from A1 could be repeated on A2 so that A2Q can go lo again. Is that how it's supposed to work or am I looking at this wrong?

Nice catch on the floating input. I don't know if I ever would've seen that. I would've just assumed it was alright since there were wires connected to all the inputs.

Let's see... I just tried adding the circuitry to reset A2 but that doesn't give me what I need either because then it wouldn't trip in reverse. I suppose I could change the value of C2 so that A2Q stays hi longer. I don't know, I'm pretty tired. Maybe the circuit is fine and I just don't know how it's used. Or maybe you're waiting for me to tell you how long we can wait while the disc rotates backwards. Well, the sooner the better of course but I could allow the disc to spin in reverse for 3 revolutions before having to send an alarm.

Thanks for all the help.

LL

--
No, I designed it for you.