digital logic delay

A couple of gates usually does the trick, but IIRR manufacturers don't specify minimum propagation delays for regular logic, and the rule of thumb is that the minimum propagation delay is only a third of the maximum, so you'd need six gates worth of delay to be fairly sure of compensating for two gates worth of delay every time.

If you are using CMOS, it might be worth thinking about a simple R/C delay - some parts specify a minimum input slew rate, which limits the RC product that you can use, but a single inverter has a gain of about ten, so if you buffer the delayed signal you can use a bigger R.C. Schmitt triggers are even better, but manufacturing tolerance on the thresholds is high enough that the delay you get has a rather broad tolerance.

You can - in theory - use R/C delays with TTL, but the nominal 1.4V threshold sits uncomfortably close to the 0V rail, and the TTL high voltage is pretty much undefined, and if you do a worse case analysis on the delay you get, you will find a 10:1 uncertainty.

Using a TTL Schmitt-trigger to buffer the delayed signal improves this, but not a lot.

If you want a delay longer than about 50nsec, the 74121 TTL monostable is a very stable and predictable device (as is the 74221 dual part). Digital designers will sneer at you if you use it. For shorter delays, you have to use delay lines - Farnell stock a useful range from C&D Technologies (was Newport) but they aren't cheap.

You have a bad design- do it over.

On 22 Feb 2006 01:13:54 -0800 in sci.electronics.design, snipped-for-privacy@ieee.org wrote,

I wrote firmware for a project where the designer had used a RC delay like that. It ended up delaying the project a couple of months.

seems that it was a much simpler solution, a dodgy solder joint, to the earth pin on the shmit ex or gate.

I hang my head in shame now

Tim.