Digital processing of analog TV broadcast

sp snipped-for-privacy@yahoo.com wrote: > Hello, >

And after Feb 2009 when the analog TV system (at least over the air) is turned off, you will want this why?

GG

I won't. But at least I'll have gotten familiar with QAM digital demodulation, filter design, DPLL's, resampling, etc. That will be useful for a long time.

Sean

On a sunny day (1 Dec 2006 11:31:09 -0800) it happened sp snipped-for-privacy@yahoo.com wrote in :

It is late, and I should get some sleep, but as to your other question as will 4x (or 3x) Fc sampling work, it reminds a bit of all the discussions about audio and 44100 samples / second, and why they went to over-sampling and now have 24 bit / 96kHz etc...

The essence of demodulating chrominance quadrature modulated signals is _very_simply_ to sample Q when I is zero, and sample I when Q is zero. In _any_ other case you will get some of Q in I and some of I in Q.

I am not a mathematician (mathemagician), but those mathemagicians will tell you it makes no difference anyways and you can sample at 3 x Fc. Later in the discussion they will claim that is because the original was shit anyways (bandwidth limited), and that may give you some idea what plays here. We have been making fun of the audio guys and gold fuses today, but I am still remembering the discussion I had in Philips about the pitfalls sampling audio at 44100. The fact we even have 96 kHz should ring a bell I, and the others claiming problems were (and are) right.

There is an other reason to do the quadrature demod analog too, for example one DVD player I have has only composite (FBAS) out, while the other also has Y Cr Cb, and you will see that a lot in higher quality systems. So if your ADC has as input filtered lowpass Y, Cr, Cb you can view these sources on VGA too, and those are the most interesting quality wise anyways. I have worked in the studios, and many here would rate a good PAL signal from the seventies, in the studio, from the camera as stunningly good! What digital has given us is to put things in less bandwidth. Mp3 and AC3 have clearly losses. MPEG2 and their similar friends (DivX, wmv) all have the nasty habit of that when you look at the person sitting perfectly still it is in focus, but as soon as that person moves the head slightest, it is out of focus. For that you have less noise and less bandwidth. BUT NOT A BETTER PICTURE. (Not to mention all the artefacts around objects).

So maybe the great mathemagicians will now care to explain where the error goes when you sample Q where I is not zero, and I where Q is not zero. I can think of some great test signals. Also for 44100 sampled audio. Be honest.

possible that I will do this later, but it won't be any time

you mind elaborating a bit on how to do the above? Is there a

Most off-the shelf crystal oscillators will do ok. Oversampling and jitter aren't correlated directly. "Oscillator design and Computer simulation" (Rhea) has a short bit about xtal oscillator design. There are many other (perhaps better) references.

I've tried using Xilinx Virtex4's built-in PLL and also Altera's Cyclone2 for video clocking and for chroma demod. Both recommend using filtering on the PLL supply. This works well enough for the video horizontal time base output to the DAC, but not well enough to prevent chroma streaking on a large display (from the sampling phase noise introduced by the PLL).

Use the crystal oscillator (un-multiplied - no PLL) for sampling the ADC. Then clock the ADC output into a FIFO. Read the FIFO with your internal PLL reference (DSP clock.) This is a standard trick.

Also, check these tricks:

What is limiting the bandwidth of your source signal? It's important to have a flat group-delay filter.

Thanks,

Frank

See, since my sampling clock has no relation to the chroma subcarrier, I'm going to have to sample in the way you described above. That is, when neither I nor Q are zero. But, as I understand it, it isn't too hard to seperate I and Q using this method (synchronous/coherent demodulation). It has to do with the orthogonality of sin and cos. Basically, your transmitted QAM signal is:

msg1 * Cos[f*t] + msg2 * Sin[f*t]

When you multiply by cos(f*t), you get: msg1 * Cos[f*t]^2 + msg2 * Cos[f*t] Sin[f*t]

Which you can use trig properties to expand: msg1*(1/2)*(1+Cos[2*f*t]) + msg2*(1/2)*Sin[2*f*t]

When you lowpass filter this, you just get: msg1/2

To get the other message, multiply by sin(f*t), giving: msg1 * Cos[f*t] Sin[f*t] + msg2 * Sin[f*t]^2

Use trig properties again to get: msg1*(1/2)*Sin[2*f*t] + msg2*(1/2)*(1-Cos[2*f*t])

Use a lowpass filter again to get: msg2/2

Hopefully I didn't make any mistakes above, I didn't have my book in front of me, but I'm pretty sure that's how it goes. Is this what you were talking about, or something else? Anyways, thanks for the continued posts.

Sean

I suppose my thinking (perhaps wrong) was "It seems likely that the time jitter in my clock scales as some proportion of my clock period. ie, perhaps a 20ns clock (50MHz) would have 1ns time jitter, while a

40ns clock (25MHz) might have 2ns time jitter. (figures are fictional, but equal to 5% of clock period). Since I'm oversampling by so much (by using a faster clock), perhaps jitter isn't going to be a problem. In other words, the guys sampling at 4* Fsc, which is around 12 MHz, can only tolerate a clock with X percent jitter, while I can tolerate almost 5*X percent jitter in my 50 MHz clock." Is that line of reasoning at least *somewhat* rational? Like I said, clock specs are not my strong point.

I will try to see if my library can get a loan of this. Thanks.

Ahh, glad to see you've tried and saved me the trouble.

Ahh, I haven't used that trick before. Brilliant.

Thanks.

In this stage, I'm literally attaching a composite video (RCA) header to my board and feeding it to my ADC (with video clamping and built in sample-and-hold, might even get one with AGC). For testing, I have an older CATV converter box with composite video output that I can use, or I can use an old console game system, etc. I'm assuming there's no high frequency left on the baseband signal, so that no further filter is necessary at all. Should be cut off at 6 MHz max, though it'll be around 4.2 MHz for broadcast signals. Should I be wary of the filters used inside the CATV converter box?

Thanks again,

Sean

On a sunny day (5 Dec 2006 10:48:08 -0800) it happened sp snipped-for-privacy@yahoo.com wrote in :

Yes I expected somebody to come with that counter argument. Although it is mathematically correct. And those filters can be made with sufficient FPGA real estate.

Now as we multiply with sin(f) etc... we need a closer look at that. You mentioned using a 'crude' lookup table? I have been thinking about that, there are algos like CORDIC too..... But also the phase must be right. And you want the values from a 20ns clock.

Here it gets tricky, and that is why I used an external 8.86 MHz xtal for PAL (fc = 4.43, you would need 2x 3.56 Mhz?). With a varicap you can then tune it so it is phase lock.... and you can make 90 degrees separated clocks from the 8.83, worked that one out in the seventies.....

I will not drop the subject, and will keep thinking about it.

It may sound like defeat to use an analog part these days (I mean not to do it all in one chip in digital), but OK, the end result counts.

As a radio man too, when we multiply frequencies, and it ain't no pure sine waves, I get visions of interference and harmonics and if the interferences of any the components result in a signal within the passband of the signal you actually want you are in trouble.

I hope your 'crude' lookup table will get you sufficient phase accuracy and no strange side effects?

After do> Yes I expected somebody to come with that counter argument.

The real estate is certainly a concern. I might not be able to use the Spartan 3 that I'm currently using.

Well, I don't know if I'd say "crude". I did mention that the table will have an N bit index, with significantly less than 2^N table elements. But don't get me wrong, the table will still be fairly large. It's just that I'm getting some extra precision by interpolating (using the extra bits). I think some people call this DDS (direct digital synthesis).

Ah, so did you use a sinusoidal oscillator (locked w/ chroma subcarrier), analog multiplier, and analog filters?

It would sure be a lot cheaper, too. I suppose I'm just being stubborn and trying to see if I can do it digitally. There are pros and cons to each way. For example, digital filters can do things that analog filters couldn't dream of doing.

Hmm, I wonder how much interference we're talking about. And, of course, whether it causes more or less problems than sampling every 90 degrees (I, Q, I, Q), with some (realistic) allowed margin for being out-of-phase. I always thought of the synchronous/coherent demodulation as being superior, but maybe not... ?

Thanks,

Sean

On a sunny day (9 Dec 2006 10:28:46 -0800) it happened sp snipped-for-privacy@yahoo.com wrote in :

Yes there is quite a bit of filers and so multipliers needed. i made a nice video low-pass, then a chroma bandpass filter. Spartan2-300. There was space left, use less poles more ripple :-)

OK, got it.

Yes and no, the oscillator is a junction FET with 8.83 Mhz xtal, but then goes into a Schmitt trigger and the square wave enters the FPGA.

I made a nice PAL quadrature encoder some time ago (years) with CMOS 4053 switches (the idea I got from some Elector article) could dig up that diagram, using a 2 inverter TTL oscillator at 8.83. In the same way you can either sample via a AD, or use drive CMOS switches to sample, here is some circuit that is analog, but digital anyways :-)

--- -------- ------------ | | | | ------- -------- A 4.43 square wave osc out from FPGA after division of the 8.86 MHz input.

- - | | | |

--------- -------------- ------------ B sample pulse from FPGA 8.86 MHz oscillator + 4016 CMOS switch varicap | \\ R ||/| |--- A ---------- \\-----------===------------------|| |------------------->| JFET | | | ||\\| | | | |--- | === [ ] | [ ] === |--------> to Schmitt trigger B | | | | | | NAND /// === --- /// |----------| the NAND output | = | | enters as clock /// --- 8.86M === [ ] in the FPGA loop filter | | | /// /// ///

Pulse B will adjust around the leading edge of A, where the voltage after the filter is 2.5V. The more narrow pulse B, the more precise the phase alignment, to a point.

So the phase comparator is digital :-) If you divide the 8.86 by 2 and / or use pos edge for U and neg edge for V (I and Q NTSC, and other frequency) you have your 90 degrees. You can then make the demodulator with these CMOS switches too :-) If you provide chroma in 0 and 180 degrees (inverted) you can sample twice as fast.

Yes I used analog pre-emphasis filters, simple CLC filters.

I dunno, lookup TDA3560.pdf, an analog PAL demodulator chip, look at the application diagram. _Worst case_ 5 degrees error, RGB out, note the delayline. They do everything in 8,86 Mhz, differential multipliers in that chip I think. That was 1980, filters what filters?

5V pp out RGB and max 150 mV left of the 8.86 (symmetry I guess). LC rules, note how the direct chroma is added to the delayed via a _trimpot_. The 90 degrees is done in the chip. Note the output transformer with 0 / 180 degrees (center tap :-) to get 180 degrees accurate chroma phases. I have that chip and stuff, was in almost every Philips color TV in those days, as a module.

NTSC is a bit simpler, omit the delay line and PAL switch flip flop, and related sync. (In PAL the R-Y modulator carrier is flipped 180 degrees each line. Because B-Y is not switched, the burst, which is simply the vector sum, swings

90 degrees. These cause a 1/2 H component on the filter of the above PLL. That is then used to sync a line triggered FF that switches the R-Y carrier 180 degrees each line in the demodulator. One could of course also switch chroma phase. When we digitise I Q (U V, R-Y, B-Y) we can store R-Y for a line, and add with the current line and we need no 4.42 MHz chroma delay line. If you do not do that then eye will have to average any error over 2 lines, this is called 'simple PAL". So maybe after you do the NTSC thingy you can start with the PAL design ;-)

I see.

:-)

Wow, pretty neat idea. BTW, do you do the ASCII art by hand or with a program? Looks pretty good, I'd be too lazy to do that much by hand. :-)

I didn't do out the exact calculations, but I seem to recall that would mean you'd introduce Sin[5 deg] * 100% = 8.7% of I into Q and vice-versa. Don't take my word for it though. Maybe I'll dig up a book or do it out myself if I remember to. Beyond this calculation, I think it's up to the physiology people to explain what the average human perceives as more offensive...

nice

Haha, perhaps I could. Actually though, I think my next project will be decoding broadcast HDTV (maybe 8-VSB, though I don't know yet, it'll be awhile).

One other question for you. I've dediced that I'm definitely using the Philips TDA8708A that you recommended. I have enough to deal with on the digital side, without worrying about DC restoration (video clamping), auto gain control, and sample-and-hold. The TDA8708A seems like a prototyper's dream come true. I have two questions though.

1 - Did you use the recommended 5th order Chebyshev filter that is shown in the TDA8708A datasheet? It's on page 17, and consists of 2 resistors, 2 inductors, and 5 caps. Looks pretty easy, being a total of only 9 passives. They also show an alternate schematic on p18, but the frequency response isn't as flat in the passband. 2 - What did you do to generate the required clamping pulses? ie, pins 26 (black level sync pulse) or pin 27 (sync level sync pulse)? I think you only have to use one of them. Did you generate the pulses digitally in the Spartan, or use a seperate analog sync extractor? I figure that I already have to look for the hsync pulses in the FPGA, so I could probably do it that way... But it might be more robust to use a dedicated chip.

BTW, I'm also planning on making a digital storage oscilloscope down the line. Would the TDA8708A function as a regular ADC (no clamping) if those two pins were just tied to ground? It's still the best and cheapest DIP ADC I can find. I got it for like 6 bucks.

Any other peculiarities to worry about with the TDA8708A, or any warnings? I'm planning to breadboard it, so I hope I don't have problems with inadequate grounding... I've heard of people using breadboards and getting huge spikes on their analog signal whenever the clock strikes. I think they were using a different ADC, but...

Ooh, that reminds me, time to order a high density DSUB header and an RCA header...

Thanks again,

Sean

On a sunny day (9 Dec 2006 19:23:53 -0800) it happened sp snipped-for-privacy@yahoo.com wrote in :

:-)

No, by hand, but i have a good editor (not emacs ;-) ). Actually about the square wave at top left that being is sampled, imagine chrominance, with burst:

|||||||||| ||||| |||---||||||||||-----|||--||||| etc |||||||||| ||||| burst color burst color

If you put this chroma into a limiting amp, the burst will come out like that square wave. The sample pulse to the 4016 CMOS switch is gated by the burst gate, that way you lock to the rising edge of the burst (in fact the zero crossing). It also works if you do not clip, but then you sample in a sinewave, so less gain in the PLL loop.

This brings me to a point i do not see anywhere in your idea: In a normal TV signal the burst (and chroma) amplitude) can vary widely (relative to the sync amplitude). For this reason there always is a 'chroma AGC', in the TDA3560.pdf you will find an AGC circuit that will support burst up from 50 mV or so (versus 300mV normal). If you digitise composite you may in some circumstances have only 50 mV pp burst, so if you have 8 bits for a full 1V video signal, 1/20 of the range is not much. Such a small burst amplitude sampled at 3 x Fc (or 4 x Fc) with only a few bits depth does not seem to help accuracy a lot?

1 / 256 = 3.9mv step, so 50 / 3.9 = 12.8 steps = 4 bits (0-15).

Am I wrong?

that is worst case (400Hz fc deviation, temp, what not).

Oops. Next we will be talking Viterbi, have not 100% hacked that myself, HDTV here used DVB-S2. DVB-S2 is a whole different beast altogether we have here:

note the link to FEC coding: it is to .7 dB of the Shanon limit!

IIRC the max sampling is about 32 Mhz, I did see your question about a 50m/s ADC in comp.arch.fpga.

I used the adapted Chebyshev, had to look up my diagram, and it takes about 2 cm^2 boardspace with the inductors vertical. Note that pad capacitance may require you to use a lower value for the 12pF, maybe 10pF.

Well, the original design (I did several tests) had syc separator with a LM1881, and then the sample pulses were generated in FPGA. That LM did not work very well, so I then just did not use the gain and sampling circuit in the TDA8708, and simply made a bottom sync diode clamp and fed the video directly into the low-pass. Then I did the sync-slicing and 2H PLL in verilog.

Just answered that i think.

Just answered that too :-) Yes but it has some weird voltage level for digital zero, not sure how stable that really is, used a 10 turn trimmer :-) You could make a J FET diff amp and interface directly to pin 20 for a scope.

128 steps up and down, V pos potmeter on front replaces my trimpot.

Yes, I think they no longer make it :-) I have 2, I can tell you were I got these

Rotterdam Netherlands).

Oh, well, ftp://panteltje.com/pub/2h/alles.jpg Note the empty LM1881 socket, the TDA is on the top left board, you can see the filter too, sorry for out of focus, fixed focus camera, could not get closer. Also note the LCD and card-reader slot. That was for PAY TV you know ;-), ran some sort of DES brute force in the Spartan. Of course not any longer now it is possibly illegal.

Yea. Lots of headers.

(relative to the sync

find an AGC

burst, so

bits depth

I think that is the weakest point in my design. Like you said, the chroma is contained within only 12.8 LSB's of the ADC. I'm just hoping for the best. I'll simulate whatever DPLL I decide on before I implement it in hardware. Probably using Mathematica, though I really should brush up on my Matlab skills. I wonder if some type of regression routine could be implemented (within reasonable real estate space) to find the optimum frequency and phase of the burst, completely bypassing the DPLL... Then just use direct digital synthesis (if that's the correct term) to generate the subcarrier until the next horizontal line. I'll have to experiment.

Yes, true. It's probably not nearly that bad. I guess this is actually the same issue that I'm asking about in the comp.arch.fpga group - I want a very low jitter clock. Though, I wonder if my design is more sensitive to clock jitter, since I need to use a DPLL on the chroma burst, whereas you can just read in I, Q, I, Q after you've seperated luminance from chrominance.

Which brings me to another question... You used the TDA3560 to generate your ADC sampling clock, correct? With the varicap for fine tuning. Did you use any of it's other features, or just the clock? I couldn't find where it outputs the chroma-locked clock (I see that it has one, but is it just internal?). But it seems to be capable of doing the entire demodulation process - all the way to RGB.

This should make for quite a challenging project! But then again, it would be nice to get proficient with something like that before the market is mature. Could be some nice opportunities.

Yes, I just realized that too! I should've ordered either 32 MHz or 64 MHz crystal oscillators! But I have a whole bunch of 50 MHz 8-DIPs, so maybe I'll just divide one down to 25 MHz in the FPGA. Or I'll just buy some more oscillators, it's not like they're expensive. I seem to be getting mixed up with one of the projects you described earlier - something about using a 200 MHz sampling clock. But surely that wasn't with the TDA8708A, right?

BTW, it actually worked out pretty well splitting my questions into sci.electronics.design and comp.arch.fpga. I've gotten really good responses from both (many from yourself).

Good to know.

sampling

That sounds like a good idea. Actually, I'd probably want to put a front-end which changes both offset *and* gain. That way the user could select the full-swing voltage range, and analyze either large or small signals, with good precision for both.

Haha, so that's why the Mouser and Digikey didn't have it. Doesn't seem too surprising, 12 years would be a long lifespan for a video IC.

Seems like we've been playing with the same toys. I actually just did a small demo project with a Panasonic card reader that we got for about $4. Nothing to do with TV though.

I've thought about trying some descrambling. The descrambling web sites all say "for educational purposes only", though I'd probably be the only one taking that seriously! I don't think I'd attempt anything with DES, but just something simple like supressed sync (maybe SSAVI). I don't plan on doing this soon, though. If at all.

I'm a bit torn between spending $6-$10 on a VGA to DIP header (could use solderless breadboard), or spending the time to solder up my own solution... Same goes for the RCA header and IDC ribbons. I know I could do the whole breadboard in a few hours, but being lazy, I think I'm just going to pay the money. Plus my work tends to be rather messy (OTOH, the picture you sent is quite clean looking). If I was

*smarter*, I'd have realized that I'm nearing the $50 range, where I could just mail-order a PCB. But I'm not. :-)

Thanks,

Sean

On a sunny day (10 Dec 2006 10:08:02 -0800) it happened sp snipped-for-privacy@yahoo.com wrote in :

Yes, anyways it is a PAL chip. You can grab the clock with any high impedance from the Xtal at pin 20.

No, that was to generate PAL quadrature :-)

Not sure wat you want to do here, I use a 15 pol D connector for RGB to the Samsung Syncmaster monitor, it has 3 BNC connectors (apart from the normal VGA) and I can select video input2 from the monitor front. Very convenient. I thought you were referring to the 90 degrees headers that connect to the digilab board.

Eh, wait till yo usee the wiring on the back :-) It is done with split flat cable.

Absolutely, it is cheaper to buy this stuff, the other poster had something like this for 37$ IIRC. But the learning experience is great. Try the scope sure, I have a frequency counter I can load in the digilab board too. If you try the scope, then you can also make an UART in HDL, and send the trace at highest baudrate to the PC, write some simple graphics display (I use Linux xforms for making GUI applications), perhaps with some buttons that the PC then sends to the FPGA board. I dunno if you can program in C. the frequency counter also sends the setting via RS232 (and to the LCD).

This has been a rousing discussion. If i were to try to convert NTSC / PAL analog to VGA i would lock my sampling clock to the color burst (like an analog set) and sample the composite at 8 samples per cycle, evenly spaced. This makes the math for the FPGA relatively simple. When you calculate the tradeoff variables of sample rate, A/D bit depth, computational complexity and various costs, this seems to be a sweet spot.

--
 JosephKK
 Gegen dummheit kampfen die Gotter Selbst, vergebens.  
  --Schiller

On a sunny day (Thu, 14 Dec 2006 06:50:17 GMT) it happened joseph2k wrote in :

Yes it makes sense to sample locked to fc. Dutch analog TV is switched of permanently now per December 11 2006.... I have ordered a DVB-T settop box (USB) that is supposed to work with Linux (I hope). That way I will be able to record digitally, just like I already do with DVB-S (satellite). Spent a wopping 29 Euro on that thing, postage is almost as high.