differential Manchester decoder and FIFO

Simple async Manchester decoder:

Make a transition detector (delay and XOR) and use it to fire a non-retriggerable one-shot on every data transition. Make the one-shot duration

3/4 of the bit time. It will soon settle down to firing on just the center-cell transition. Use the one-shot output to clock the data.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit must be able to decode without any changes with this condition.

Sounds like FPGA turf, then. Grunt work.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

FPGA Look at the HD-6409, I've used this in another life. You'll have to do a auto baud measurement on the sync data, the 6409 has a pre-amble to sync the data clock. There is no whay to sync with out missing the first bits. Cheers

That could be tough. I did a design similar to this in an FPGA. It received a simple bit stream and had to sync to the transitions. But it had a timing setting to establish the base frequency approximately.

This design used a locked loop to adjust the NCO to the bit rate. Since the base frequency was set by the user the search mode is not overly aggressive. In your case you might need to use a rather aggressive search mode to set the base frequency very quickly, or even do a frequency measurement for a direct setting.

Do you have a spec on the data stream format you will need to sync to? As others have indicated, there should be a preamble which would be a stream of bits which produce a single transition in the Manchester encoded stream. Knowing the length of this preamble will give you an idea of how quickly your circuit will need to adapt to the data frequency and lock up to the data stream.

--

Rick

An FPGA could just count the widths of the high and low signals, with maybe a

100 MHz clock, and then do the math.

Hey, determine the probable bit period, not hard to do, and then fake my 3/4 period one-shot decoder.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

Thanks for respone.

I've never done anything with FPGA (and CPLD). I was thinking about Lattice. I don't know whether this is a good choice. I don't know what to choose (design software and device).

Very interesting, but max. data rate = 1Mbit/s.

Missing the first bits (even ~1000) is no problem.

There is another M en/decoder that runs at 10mhz. HD-15????

Cheers

I puzzled over you might automate determining the data rate. Turns out if you do an integrate and dump on the Manchester signal...

you get an average value proportional to data rate.

Since you have a very wide frequency range I'd suggest AGC'ing the integrate current to keep the integration from clipping, then use a replica of that same current to time the 0.75*TB one-shots to restore the clocks.

All Analog ;-) No FPGA's. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I'm not so sure now. I think it needs some further math :-( ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Yep, It's good. Got myself confused there momentarily. It works. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I didn't analyze your circuit entirely, but the XOR gates with the shift register seem to be a LFSR or something similar used to produce a pseudo random sequence. No?

So how does your circuit work if the data stream is *not* pseudo random? That is, how does the data pattern affect the voltage? Looks to me like this circuit detects the rate of transitions rather than the rate of the clock which is what is needed. I think it is very sensitive to the data pattern and will not produce a constant voltage if the data pattern is varied while the clock rate remains constant. Try your simulation with an all 1's data pattern and an all 0's data pattern and see if the average voltage is the same. I think it will be 2:1.

On the other hand an all digital approach can be made to work.

If the OP needs some help with the problem I am available.

--

Rick

I found HD-15530 and HD-15531, both under 10Mbit.

S/PDIF.

Lost of first bits is no problem.

Thanks, but I don't know why there is a lack of images.

Try this link to the issued patent...

A digital implementation similar in concept to my analog posting. ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Yes , I am the author of that patent , and the concept came from an analog implementation that is similar to your description.

Bob

So what is the problem exactly? Do you not know where to begin? The patent shows one way of doing it. There are other ways of cooking the goose. Do you understand the separate functions that are needed? Clock rate detection, bit synchronization, data extraction?

--

Rick