Hello all,
Could you suggest a reading about the effects of clock jitter in delta-sigma ADCs ? How does it affect SNR, THD, IMD, SFDR ? For some reason, this practical aspect is not mentioned in the ADC datasheets and manuals; the typical phrase is "good quality low jitter clock should be provided", whatever it means.
It shouldn't be too difficult to figure out the numbers by hand; however I am pretty sure there must be a closed form solution already.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant