d-flop one-shot

I get better hits using the term "monostable":

Fig 9 is about as simple as it gets. I don't understand why the extra flop and the low pass and stuff after the button in the link you posted, it's like they never heard of a passive differentiator before.

One way to shorten a pulse derived from a clock signal is to clear the d-type with the clock signal. Suppose you have a 1 clock cycle pulse produced by a d-type. Connect it to d on another d-type, connect the clock as usual but also connect the clock to /clear A 74HC74 d-type will clock and Q will go high but then it will be cleared by the clock going low and so Q will go low half a clock later.

You can debate whether or not this violates any setup/hold or other timing requirements and you can always delay the /reset signal with a gate or two if needed.

I've seen this work fine in an experimental design using 74HC74 with clk and /reset connected together.

Yikes, 36 years old. CD4000B logic.

I like d-flop one-shots because they are fast, truly edge-triggered, and can be gated with the D input.

But RC feedback into a reset input is risky at best. Some flops simply won't work that way... they hang up.

That assumes that the going-away prop delay of the reset path is faster than the clock path. Might be for some flops.

Yes it does, which is one reason I've never used it in a production design, but I have seen it work fine in an experimental design.

Is this in furtherence of your TDR experimentation? I can't think of anything else a one-shot is useful for.

Phil is doing a TDR project. I'm mostly doing slow precision stuff lately.

I am planning a few new products, and one is a sort of precision pulse generator. I was thinking to have the "HIT" flop, the first trigger recognizer, be the one-shot. But it's easier to put that inside an FPGA. The problem with FPGAs is time jitter, from all the routing crosstalk and clock feedthru and ground bounce and power supply sensitivity. Maybe they can be managed.

I tested one Xilinx chip for pin-to-pin delay sensitivity vs core supply voltage. It measured 70 microvolts per picosecond.

Some people think one-shots are evil, but I like them.

Probably not. Signal routing is a problem that's hard to manage if you don't have lot of control over where the signal goes, and can't add shielding tracks alongside sensitive signal paths.

I had one famous success when I was in the Netherlands, when I added an ECL front end to a basically TTL delay generating device. Changing Vcc levels shifted the output edge by an appreciable fraction of a nanosecond in the original TTL-only system. Shifting the edge-generation into ECL and taking the TTL output edge from an ECL-to-TTL converter reduced the timing jitter to undetectable levels.

They certainly can be, but they can equally be very useful.

You'd be well advised to look carefully at the emitter coupled monostable, and work out exactly what it does when it starts generating it's output pulse.

This isn't trivial

If the two transistors in the simple emitter-coupled monostable are BFR92A parts it can produce a one nsec wide output pulse. It can also oscillate if you don't manage the base driving impedance carefully.

Faster parts could do better, but can be even harder to keep stable.

So don't google that.

Any electronics that is controlled/triggered by a manual press switch needs to recognize and address the limitations of that hardware.for predictable operation.

A suirable topic for electronics 101.

RL

I just invented a search engine that delivers no results. It will improve the world.

SN74LVC1G123DCU is a nice little part. Good for flashing LEDs and such.

The supply to delay variation in the Greenpak SPLD 16 bit counter configured as a one-shot is around 10, in simulation anyway..

I'll try to measure it this weekend, I'm interested to see. What general length of one-shot are we talking?

In one application, just a few nanoseconds. I figured that I could run \Q to \Reset through a gate or two.

I would use the D input of the flop for "pulse picking".

Yeah that's tough cuz even at 50 MHz 1 clock is 20 ns and at low counts there's also a variable offset a la:

pulse length = [(Counter data + 1) / CLK input frequency – Offset],

Where Offset could be in the range 10s of ns at that clock frequency, worst case, independent of supply

A 1 ns Tiny flop and a 1 ns gate (or even a PCB delay line) would make a gated one-shot that would run at a couple hundred MHz.

Connecting \Q directly to \R would be interesting. I should try that. The 1 ns cmos flop is NC7SV74.

What about using a PCB delay line, and diff amp and driver to take the difference between a short and long path

What about using a PCB delay line, and diff amp and driver to take the difference between a short and long path

That works, a delay line and some fast gate. But it doesn't have the clean edge response of a proper one-shot, or the D input that can be used for gating.

The delay line can be a few gates, so you can do the whole thing in one quad gate package.