I'm sure someone has an quick answer for this. I'd like a simple circuit or a part that produces a pulse -- basically a one-shot -- with both a rising edge and falling edge input signal. All the multivibrator ICs I have seen will trigger on rising OR falling, but not on both. How can I get a trigger on both?
I would use a quad XOR to build an edge detector: wire three of the XORs as non-inverting buffers and put them in series, connect the output of this s eries string to one of the inputs of the fourth XOR, and wire the other inp ut of the fourth XOR to the input of the first of the three series XORs. T his will produce a narrow pulse on both polarity edges of the input. The w idth of the pulse will be the propagation delay in the series string (when I did it a long time ago with standard TTL, the spec sheet gave the delay a s 10ns/gate, but when I measured it, it was closer to 3-4 ns). If these pu lses are too narrow, you and increase the propagation delay by putting some small capacitors to ground at the interior nodes of the series string.
jfeng has suggested feeding the two inputs of an XOR (such as CD4070) with the direct signal on one, and a delayed signal on the other. You can get that delay from propagation delay of multiple gates, as he suggests.
An alternative (which I first saw in the "CMOS Cookbook" by Don Lancaster) is to use a simple RC delay and a single XOR gate. You connect the signal directly to one gate input, and through an R to the other (with the C going to ground).
This gives you some adjustment flexibility for noise rejection, etc, if you don't mind adding the discrete RC parts. You also may find other uses for the remaining 3 XORs in your CD4070 (or whatever).
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No, not in my close family line. Legend has it there were "northern Beesons" who went to Ohio after the Revolutionary War and "southern Beesons" who went to Alabama and elsewhere. All the well-known Beesons (except for Chalkley Beeson, my great-great uncle - Google him) came from the southern line.
Thank you all for your suggestions. I like the XOR approach, especially the single gate with an RC delay. My timing requirements are not super tight. The output needs to clock a flip-flop that can handle up to 175 MHz - so around 6 ns pulse width minimum. My application will work just fine with 100 ns -- or even wider -- pulse widths, so I am thinking a 1k resistor and a 1 nF cap as RC.