Conversation with a new circuit designer

On a sunny day (Sat, 04 Jan 2014 08:23:26 -0500) it happened Phil Hobbs wrote in :

I dunno, been out of that for some time. In those day we had every chip from every piece of equipment in stock, a requirement. Sure in emergency you would swap boards, but with WHAT if everything was in use, so usually repair on component level. I remember one day, Oh well, 20 minutes.. to find and repair a fault in a complex piece of video encoder from an other country (say world), did it.

Oh yes.

It doesn't confuse me. And the hand-drawn doesn't look exactly like the CAD library part, although I do make it very similar.

Physical pinout makes the signal flow terrible.

That's missing a few fundamentals:

Title block, saying what this is and who did it Drawing number and revision Date of last change

On my hand-drawn schematics, I can expect them to change a few times in the first days. If I transfer a copy to Bratinella to begin CAD entry, I make sure that's dated. If I make any changes, which I usually do, I note and date the changes on my hand-drawn original and give her an updated copy.

Once rev A is fully entered and reviewed and released, the vellums are no longer updated, so are archived in a big flat file.

We have hundreds of active PCB designs, each with revision letters and dash-number versions, BOMs and ECOs and test procedures and manuals and NEXT files. All that has to be managed very carefully.

The CAD schematics certainly do.

I don't assign pin numbers because, for things like dual opamps and FPGAs and resistor packs, The Brat assigns them. I let her decide things like discrete/pack resistors, FPGA pins, things like that, to optimize the PCB layout. She's compulsive about symmetry and flow and manufacturability. We'll check the hell out of it later.

Here's the one I'm checking this weekend:

(Looks simple, because the microZed does most of the work)

It's up to rev 19 now. It will be formally reviewed on Monday and formally released on Tuesday, as rev A.

The CAD schematics are formally released. My hand-drawn vellums are just the second step in the design process. Scribbles on whiteboards/notepads is the first step, but they get thrown away. I keep the vellums.

We print schematics on B size (11x17") paper. Minimum text is 200 mils and min line width is 20. It's very readable.

On a sunny day (Sat, 04 Jan 2014 07:56:46 -0800) it happened John Larkin wrote in :

Sure, but this was for me myself in person only. I have to build it, fix it, even if I find it 10 years later. We had a drawing department that I would hand this sort of stuff... :-) I once gave something like this to a PCB house, lot more complicated though, 'no problem' they said.

My pencil drawings are kept in a safe place, obviously will be worth millions in a few years, you can buy these as investment. It beats Rembrands.

Yes same with software.

On a sunny day (Sat, 04 Jan 2014 08:12:48 -0800) it happened John Larkin wrote in :

Yes,hard to judge, maybe rotating the chips and putting them closer to the edge would shorten tracks, no idea about those signals, seems the left side has less connections though, so why not.

Yes, that looks nice!

We have a Sharp office copier that's networked. It will copy, scan stacks of paper to TIFF or PDF, and it's a really fast printer for B size schematics. Toner comes in big cans so costs a fraction of inkjet or HP-type toner cartriges. No color, but our schematics are still all b+w.

And of course I have a classic ammonia-type Blueline machine to copy my D-size vellums. And electric erasers and pencil sharpeners.

Our building was designed so that I can sit at my drawing table and look out at the rain (and the lighthouse.)

works great if you're trying to greatly reduce gain...! :)

Jamie

Jan, I think you are missing the difference between the formal schematic (which has pin numbers) vs the hand drawn schematic without pin numbers. It is understandable that he does not designate pin numbers at that point.

A schematic which shows the parts the way they are physically is a blessing. It is much easier to find the right pin to probe. Often you can just count 5 pins up from the decoupling capacitor in the middle or something like that. Otherwise you'd need to consult the datasheet and count all the way up or down the side of a QFP200 package to find the right pin.

I usually use netnames for the power supplies on parts with many pins. Plastering a schematic with power symbols is not going to help.

We rarely use high-pin-count leaded parts. They are hard to solder/inspect/probe. Probing is risky. Big parts are now mostly BGAs, which, thankfully, can't be inspected or probed.

I generally pack more into a page (less white space, larger symbols, or something), but it looks something like that.

No problem for a pass element. The issue becomes larger packages. QFP144s get to be a real mess.

"We" create our own, too, but *I* get no say in them (with the exception of BGAs). No one in the US gets a say and they can change out from under us. :-(

We usually do the second, for SSI sorts of things. If there is only one "circuit", power and ground are on the main. If it's a larger chip (not multi-circuit SSI or BGA) it's all on one symbol. BGAs I break up so power is on it's separate "section" so I can put it on the power page.

Depending on how it's "CADed", that's fine. I *don't* like connections by reference but yours isn't that bad. At least you don't have signal names (used as connections) in the middle of a net.

It is. Now do that with a QFP-144. Gack! ...but we have no control over that.

If it's too messy, you're asking for mistakes. It's very difficult to do any design reviews, as well. Not good, even if it is "just for a netlist".

Better for design reviews.

That's a theory, but then do they all have to be placed on the page as they are on the board? Orientation? What if I flip one? ;-)

Management rules.

It would be good to have the fewest errors. There is also the issue of the customer understanding what you've done. Schematics for the ADI development boards, for example, are a rats nest (not to mention their habit of stamping "CONFIDENTIAL" in 100pt. type, covering everything).

How do you do off-page connections if not by reference? Sometimes "off page" connections on the same page help to keep things neat.

I agree that plunking a net name in the middle of a wire, and doing off-page connections, is terrible. Off-pages should be explicit connections.

I've seen schematics that use a big meandering bus on every page, with all sorts of random signals entering and leaving the bus. Worst of all worlds.

Something like an FPGA is created with separate boxes/banks: a few i/o banks, one overhead/configuration, one jtag, maybe one or more just power and ground. It stays that way on all schematics.

Something like a RAM or ADC or DAC, we create with a nice flow... inputs left, outputs right, power up, grounds down. Usually just a rectangle.

If you're the design engineer, take control!

I assign pin numbers on opamps (again, no choice) and tell the layout person to assign them any way he chooses. If he wants to change packages, I want to know, however.

I've had pin numbers on diodes get us in trouble. I finally had the librarian settle on pin numbers 'A' and 'K', instead of '01' and '02'. It seems IPC and manufacturers disagree.

Then, isn't almost always done at a depot level with ICT? People are expensive. OTOH, we debug boards because the failures are much higher on prototypes and the early boards are often a scarce resources. We can follow our schematics, though. ;-)

We use the '.' but anything less than one has a leading zero. It's also fixed point type so the decimal point is obvious. *I* use that nomenclature for voltages, though (e.g. 5V0).

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

Now, do you mean the thick, logical bus kind, or do you mean, a bunch of individual wires, flowed together for maximal confusion?

Because I've seen the latter, and it's quite terrible. I have suspicions that service engineers go out of their way to make schematics unreadable ("physical" layout, bad wiring, complete dearth of net names, etc.), presumably to maximize the profit of their repair division.

Too bad it doesn't help anyone when it's 30 years later and the company doesn't exist anymore...

This is standard, e.g. for Altera's stuff, at least what I've seen in Altium's libraries. Guessing the PADS versions are very similar.

Tim

With off-page connectors. Just naming the nets the same is really poor practice but it's all too common.

Right, with specific connectors indicating the direction of the connection (source/destination/bi).

Random signals, yes. Related signals, no. Meandering, well, if you can't control where the chip I/Os get placed, sometimes there isn't a choice.

Yeah, but even that can get really messy. I'd rather create a symbol for each logical unit, no matter how it crosses banks (often several banks use the same I/O). I'd rather have like functions in the same block so excess off-page connections can be avoided.

That's exactly the way I do it, when I have a choice. Even with FPGAs.

Not possible. The librarian has that control (and can change symbols and even footprints) that are already in use.

One thing I was trained *NOT* to do at Marconi drawing school (when I was an apprentice over 40 years ago) was to have 4-way connections, a convention I carry through to this day!

Even though they are dotted on your diagram if the dot becomes faint the drawing can be miss-read.

Andy

On a sunny day (Sun, 5 Jan 2014 11:03:59 -0000) it happened "Andy Bartlett" wrote in :

Right I 100% agree, always offset a bit.

I used to make sure there were offsets but it takes way too much space on crowded schematics. 40 years ago we didn't have the tools we do today. It sorta the same as the "rule" about two spaces after a period (I still do it ;-).