complexity, perversity, general evil

On Thu, 22 Nov 2012 14:44:38 -0800, John Larkin wrote: [snip]

Watch out for the SSEL pin. If you let the SSP controller drive it then you are good for only a single 8 or 16 bit transfer. Some times everything will work OK but there is some timing issue with loading the fifo where the controller will deassert the SSEL pin. I found that even using DMA transfers it was not completely reliable. You need to drive this pin with software. Just change the pin config for the SSEL pins to be GPIO.

We are using a gpio pin for the Cyclone nconfig, but maybe they aren't allowing enough time low (to really reset it) and then high, before starting the SPI bit stream. FPGAs sometimes do complex things at config time.

Still, the three month tau is interesting. It's likely inside the FPGA.

Living critters are interesting. Genes are full of conflicts and defects and random assembly, but things usually work.

I tried local heating of various chips, no result. It would be more difficult to, say, heat one chip to 120C overnight to see if that breaks it. But I might try that on just the FPGA. I'd need to keep the FPGA hot without much heating nearby parts.

BGA package? Maybe bad solder joint or some pin floating that should not be. To me sounds like a cap or power plane discharge issue and maybe a pin not connected like you think. It might also be that the "good" board is really bad and something that is wrong with it is making it work. Your "bad" boards are actually doing what you ask of them due to a design problem. Maybe a ground ball not grounded like you think it is. I would go through the FPGA block pin by pin, net by net. Hopefully your DRC would catch it but check your layout again.

One more thing to be aware of, at least on the 17xx (I have not used the 3250). The flash accelerator fetch can screw up a software timing loop if the loop crosses a cache boundary.

se

Some 30% of human conceptions that make it to implantation expire within the first trimester - early miscarriage.

If your gadget had been gene-based, your production line would have had a lot of discards.

Did you figure this one out, John? If so, it'll be one for the tricks bag.

Cheers

Phil

We fixed it, but we never figured it out. The Cyclone FPGA seems to be going busy for about 800 milliseconds after powerup. Its nstatus output, which should be low (since nconfig is low) goes high for about

It's a mystery why this happens on almost all units of two different products, and never happens on two others. And why it only happens on first powerup of new (or baked) units, or after some months of power-off storage.

The uP code crash was a red herring. It crashed because the FPGA wasn't generating the 50 MHz Ethernet clock.

This will bother me for the rest of my life.

I fixed a stereo amp for my high school English teacher, back in the

e,

ew

s bag.

The biasing network in a Class A/B amplifier sets up the standing - bias - current through the output stage when the output isn't delivering any current. It needs to be high enough to keep both sides of the output in Class A when the output is delivering small amounts of current. It's usually designed to track with the average temperature of the output transistors, and should include a trimming potentiometer to allow adjustment for the actual Vbe drops of all the transistors involved - typically five.

Designers are prone to set the standing current too low.