Common collector Colpitts oscillator frequency formula

Low harmonic content, possibly? The means of limiting will affect that.

Usually not important in the sense of squaring up a signal. The majority of commercial precision applications require a square clock. Sine wave output options are not requested much nowadays.

Duty cycle can be important, i.e 50% which means low even harmonics.

-- Kevin Aylward

Phil is an analog guy, and has posted about highly linear multiplier chips, so I suspect he values sine waves more than you do. The means of amplitude control have a big effect on sine purity.

Once you have a good oscillator, it's easy to get whatever waveform you like. I was merely pointing out that there are two amplitude-limiting mechanisms in BJT oscillators, namely E-B cutoff and C-E saturation.

Saturation is slow, on account of charge storage in the base, and that makes a mess of the phase noise of the oscillator. So you want to make sure that the amplitude is limited by cutoff instead. It's just a biasing issue.

The amount of virtual ink that got spilled over misunderstandings of this simple point was fairly epic.

Cheers

Phil Hobbs

I.e. the two extreme ends of the transistor's operational region.

I can't explain why Steve had trouble with that idea, but I don't think anyone else did.

Or use AGC, per a long discussion I started and JT responded.

I didn't misunderstand it. I just pointed out that Kevin's list of "important characteristics" was incomplete.

Right, as long as the AGC mechanism itself is quiet.

Cheers

Phil Hobbs

My point was simply based on working as an analog designer of high precision oscillators ASICS at Rakon for the last 10 years. We have Oscillators that have various options such as Sine wave, CMOS etc, but its only a small percentage of customers request sine wave outputs. This has led to later asics having that feature removed.

In practices, any sort of fancy amplitude control pretty much invariable ends up adding excessive phase noise into the system, so its not done. Simply clamping/limiting is usually the best. I have spent some time looking at these issues :-)

-- Kevin Aylward

I.e. the two extreme ends of the transistor's operational region.

I can't explain why Steve had trouble with that idea, but I don't think anyone else did.

Or use AGC, per a long discussion I started and JT responded.

I was just high lighting what the bulk of telecom, navigation etc companies actually buy, in millions of units of.

-- Kevin Aylward

It might, but depends on the specific design. For example in standard substrate asics, if an npn transistor saturates, its parasitic pnp turns on, and its 1/f noise current injects significant noise.

I disagree as a general principle. It depends on the specific design. I truly can't post the details for propriety reasons. I can say that I have a very good understanding of what the main stream commercial precision oscillator vendors have for phase noise performance. I have a design that is supply limiting, yet is of the order of 12 dB lower 1/f noise than anything else out there. Its quite a subtle design using a combination of features to prevent 1/f noise up conversion.

General PN stuff:

-- Kevin Aylward

Kevin,

Thanks for this.

A friend and are trying to learn from this page, but your image under "ISF Oscillator Schematic" is rendered as a GIF that's far too small, which makes it hard to follow the design.

Is it possible that you could update the page with a larger version of this image?

Clifford Hetah.

Here's simple Colpitts 150MHz but it needs a buffer as 10pF probe affects the feedback.

t>his image?

I have original docs with all the stuff in it scalable fonts etc.. Send me an email and I can send them to you. My email is on my websites.

-- Kevin Aylward