I've been thinking about this
as a roughly 500 MHz clock oscillator for some digital stuff. My FPGA guys claim they can accept that as an LVDS clock input. The comparator would be LVDS in and out, FAN1101 maybe, if it is really fast enough.
So I have a question for some more RF-ey guys than me. Q1 furnishes negative resistance so oscillation builds up, pretty much a sine wave. At some point R1 and D1 load the negative swing and add real loss, so it stabilizes at ballpark 1 volt p-p centered on ground, just enough net negative resistance to match the losses of the transmission line.
If the gain of Q1 is high (low R2) and R1 is small, it clips pretty hard and the sine is flattened. It's flattened identically on both the positive and negative peaks, which confused us for a few seconds.
So, given all that, how does hard clipping affect the phase noise, as opposed to softer limiting or, ultimately, some super linear AGC loop? I want a lot of swing into the comparator, 1 volt p-p maybe before its ESD diodes conduct, and I want the thing to oscillate reliably, which suggest sorta hard clipping, with some visible flattening of the sine wave.
No matter how much gain we have in Q1, and how hard we clip, the txline still sees exactly as much negative resistance as it takes to equal its equivalent resistive losses. So as regards phase noise, does it matter how hard we clip?
I did google this some but didn't find a good answer.