The system already has a clock, and the ring oscillator/counter are buried somewhere deep inside the FPGA fabric. The incremental EMI will be trivial.
A simple diode path is all
Plus an external ADC, which may or may not be available
In just about any chip design review I suggest this
The best solution would be to include an SPI temperature sensor, available internally and externally. Core voltage *can* be tweaked to offset prop delay TC. That's actually done in some ASICS.
But most users don't need to flatten prop delay over temperature; they only need to be assured that their logic will work worst-case.
John