Cirrus Logic DAC requirements

It's probably assumed if you're working with an audio DAC that you're familiar with the clocks. LRCK *has* to be synchronous with MCLK - that's the whole point of it.

I haven't used I2S format - just 'normal' dsp left-justified format but I'm sure the I2S data is pumped out at the same rate and hence the receivers need to be synchronous too. Certainly do with left/right justified serial data.

Graham

An update to my last post, I have been advised on how I can meet the sample frequency, by setting the CPU's MCK master clock divisor registers, which reaches the memory controller and the embedded CPU peripherals (SSC).

The sample (LRCK) frequency can be flexible, say 44.1kHz or 48kHz, when further divided in the SSC from the MCK, but there doesn't seem to be any way of outputting a (256x or 384x faster) clock out from the processor, as I can't find a way to route this MCK signal out to my DAC.

and Pooh bear you are right, it does need to be synchrnously derived, it is that which I need.

In short, the DAC needs:

256x: LRCK = 48kHz | 44.1kHz (LRCK is sample frequency) MCLK (12.288MHz) | (11.2896MHz)

or 384x: LRCK = 48kHz | 44.1kHz (LRCK is sample frequency) MCLK (18.4320MHz) | (16.9344MHz)

I have the I2S controller, but not the MCLK for the DAC!

What about an external clock oscillator, that you derive all three of them from?

Of course, a schematic and link to that data sheet and whatever CPU you're using would help. :-)

Good Luck! Rich

Talking to TI's European audio support guy this afternoon we briefly happened upon the subject of clocks - notably clock recovery. He mentioned there are some dedicated clock oscillators to do the job the OP wants ( but there's sod all that usefully recovers the clocks from a serial data stream ). If not TI, I'd guess Cirrus's Crystal division will do some suitable clock generators..

That would be interesting.

Graham