hai, iam designed a triac circuit to controll a capacitive load. The triac used is BT139. I am not included a snubber circuit.Is that necessory for capactive load?? Then how is the design the snubber components?? iam expecting a positive reply..
ringing / high voltages created by inductors (dI/dT).
The dI/dt rating is more likely to be important if a capacitive load is being switched. An inductive load tends to be a gentle one with respect to dI/dt since inductor current is hard to change fast.
(To the OP:) You need to be sure that something limits the rate at which current rises when the triac is first turned on. Until it has been fully turned on, it can be harmed by currents that are well within the device current rating. Inductance is often added in the load circuit to limit dI/dt to the device rating. For your BT139, that is 10 to 50 A/uS depending on the load current direction and the gate drive polarity.
Perhaps it may be possible to fire the triac near the zero crossing of the mains voltage. In this case the current will be limited to C*dv/dt. This assumes that the initial charge on the cap is zero of course :-)
I suppose it depends if the OP wants an "on-off" control, or one with a variable firing angle. If it is an on-off situation, the OP might consider a solid state relay.
Alan R. Turner | Live never to be ashamed of anything you do or say.
To reply by email, remove Mr Blobby.
"Snubber" circuite are used when inductors are being switched, due to the ringing / high voltages created by inductors (dI/dT). So.. look at a circuit like the following: power supply feeds a resistor to a switch to ground (the triac) and the capacitor is in parallel with the switch. Start with switch open - capacitor charges to supply voltage = is triac rated for that voltage (or more)? Then close the switch (turn on triac) - large current flows from capacitor thru triac, limited only by inherent resistances of the circuit = is the I*I*T rating of the triac exceeded (pronounced "eye squared tee")? Sadly that data appears to be very absent these days; 30-40 years ago that crucial design info was *published* as a part of the data sheet specification of (power) thyratrons, ignitrons, SCRs and triacs. That info is similar to SOAR or Safe Operating Area in power transistors and is absolutely necessary so that a designer can prevent device destruction.
Another example of Brasfield moronic advice. Hey , Larry, you try hard to be the big anal-yst but it's not working too well for you- you just don't have the evolutionary endowment. To listen to a moron like you one would suspect that a 50A/us current rise limiting at 1mA would blow the thyristor...what a confounded idiot and fake you are. It looks like you are a total failure at actually understanding anything. All you know how to do is regurgitate specs you can't fathom- pathetic.
A bit misleading in the OP's case. The di/dt issue addresses the case of repetitive low-gate di/dt drive while expecting fast triac current rise. This involves conduction-spreading, an issue that's reduced with more aggressive gate drive. Usually a more relevant issue arising from high peak currents when switching capacitive loads is the need to model the transient power dissipation, and analyze this against the "Transient thermal impedance" curves. This reveals the triac's transient thermal mass, which must absorb the transient energy without exceeding Philips' modest 125C maximum junction-temp spec for the BT139. As with the dI/dt issue, adding series inductance is sometimes helpful because the part's available thermal mass increases by the square root of the increased duration of the heat pulse.
Mr. Baer's post to which I was responding adequately mentioned the pulse energy issue. I don't think it is misleading for me to add another consideration, especially when I indicated agreement with the rest of Mr. Baer's advice, including that issue.
Have you seen any data on how safe dI/dt varies with gate drive? My understanding is that the gate does not reach all portions of the junction pair that is being turned on and that conduction spreading is what gets most of the device area conducting. Given the relative magnitude of the load and gate currents, at least when dI/dt is an issue, I would expect the spreading rate to be independent of the initial gate drive.
Larry Brasfield wrote: [...snip moron Brasfield editing...]
You are running 10/10 on worthless and inapplicable "advice" so far. Keep using your little specious pseudo-intellectual vocabulary- just love it- a sure sign of a nobody trying to be a somebody the way you misuse those words. You are a good-for-nothing loser. You should find companionship with a certain sub-population of similarly worthless trolls on SED- lots of non-degreed technician types here- long on OT opinions and sickeningly short on anything worthwhile or constructive.
If you study various manufacturer's writings on the issue, you'll learn that high-current fast-risetime gate drive is important in high dI/dt applications. I haven't made comparative measurements myself, but I've read enough to give me respect for the argument.
ringing / high voltages created by inductors (dI/dT).
I can see that one might think that dI/dT is important, but I*I*T is far more important! If you check out the units, (I*I*T)*R ==> energy (aka power). And it is a high amount of power that can literally vaporize devices.
later claim some mousy excuse whenever anyone points
False. My first post on this thread raised a single issue without making any claims that other issues did not exist or matter. To the contrary, I acknowledged the existence and relevance of other issues with my quoting note: "(Cut the rest, with which I agree.)"
Many people consider the excision of material irrelevant to the points being made to be good Usenet practise, as do I. Your transformation of it into an excuse for spew is pathetic.
I doubt it for reasons I doubt you could discuss intelligently. However, the notion of charging the diffusion capacitance is rather amusing. Do you think it exists before "charging"?
Your obsessive repetition is fascinating. Again, No.
Hey, idiot- this is your standard cop-out: first you pretend to post an all encompassing description and then you later claim some mousy excuse whenever anyone points out your omissions. Looks like you have a pat set of excuses on the ready- along with the "I have nothing to prove" weaseling- you are a worthless usenet troll and snake who gets whacked early every time.
Think it might be a diffusion capacitance charging issue, retard? Your confusion here does not gel with your claimed prowess in that eb-zener "puzzle" you were pseudo-intellectualizing over earlier. It is a very sorry situation when a person your age insists on living in a fantasy land when you should be reconciling your ignorance, incompetence, and overall worthlessness as a human being. Go away and stay away.
Ehhh- shut the F__K up, you whining little fake- looks like you're drowning, poser, get a clue.
You have this persistent hang-up on intelligence because you do not possess any- tough sh_t pseudo-intellectual, you will just have to work with the hand God dealt you, and that "ain't" much...
Carry on, little trooper, just like your mommy and daddy taught you...you're essentially a little weakling loudmouth and a wet rag as an engineer poser...and guess what?- mommy and daddy were wrong- you are truly a p.o. crap...
In crowbar applications, the worst capacitive load case, the gate drive really should have a rise time under 100nS. You want to hit the part with nearly the makers limit for gate current.
Also, the inductance decreases the energy that has to be eaten in the SCR. A small impedance prevents the current from rising to a huge number until after the voltage on the SCR is decreased. The inductor doesn't even have to remain an inductor at the full current. An inductor that is lossy to high frequencies and saturates as the full current seems to work fairly well to keep an SCR alive. I've used a 0.25 inch toroid of 3F3(I think from memeory) material with a few turns of #14 wire. The current waveform looked something like this:
^ Way up off screen ! on the scope ............*...... ............*...... ............*...... ............*...... ............*...... ............*...... ..........**....... .......***......... ...****............
I think what happens is that the lossiness of the inductor lets an initial current flow because the loss makes it look like a parallel RL circuit. This initial current gives the SCR a chance to have its morning coffee before it needs to do any real work.