A crazy way to save (area) space on resistors/capacitors is to put them on edge.. Other crazy ways is to have pads the same width as the leads of SMT ICs and placed so the lead ends co-inside with those pads (solder curvature on inside & under part); combine with 5 mil tolerances and running as many traces underneath ICs you dare can save a lot of space if there are a lot of similar PKG parts on the board.
Yes, they are. And I can even communicate with the Erfurt guys in German :-)
Did you use it with the HV extension? If so, how high did you guys go in operating voltage?
I had a nominal 5V system with most of the chip area, plus a buck switcher producing the 5V from 30V input... with pass device, inductor, capacitor, and fly-back Schottky external... so I only used the XH-035 components for drive, current limiting, etc. ...Jim Thompson
What process would that have been? I only find...
5HP: 3-metal, 1-poly 6HP: 5-metal, 1-poly 5AM: 4-metal, 1-poly 5DM: Added dual/thick top metals 6DM: Added dual/thick top metals } 5PAe: 4-metal, 2-polyMaybe you are remembering incorrectly?
In searching thru my IBM data I found an E-mail you sent to a co-buddy (the other Phil), "The circuit you sent me looks very elegant, as I'd expect from Jim Thompson"
I guess too much exposure to nikraL has changed you opinion?
(Backwards to avoid my own filter :-) ...Jim Thompson
My opinion of your technical competence remains high--why wouldn't it? I just wish you and some others didn't act like middle schoolers on SED, because it's so tiresome. Your being so pleased with yourself doesn't help either.
I'm looking for the picture, but for now, here's a link showing an old
130 nm IBM process with eight metal levels, including optionally three fatwire levels as I mentioned:Wikipedia also agrees with me:
"Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps."
Cheers
Phil Hobbs
I have successfully stopped that tit-for-tat. Have I not? Unfortunately very little technical content has come back. I'm hopeful that it will return.
Pleased with myself? Of course I am. I'm about to achieve my 200th successful chip design (not even counting the ones I simply provided a cell or two).
Is "pleased with yourself" now a criminal offense... probably is now under this "share the wealth" regime.
Thanks! Maybe they didn't offer it outside of IBM? ...Jim Thompson
h
Unlikely.
Jim's mirror tells him that he has completed 200 successful chip designs. He thinks that this makes him a master chip designer. In fact he's a competent journeyman. There are master circuit designers around, and they produce better chips than Jim.
Jim's high opinion of himself is his way of coping with that reality. It's not a good way of coping, and makes him more obnoxious than he needs to be. Isaac Asimov had the same kind of problem. He was good, but not great - not Kornbluth, not Pohl, not Neal Stephenson, not even Ian M. Banks or Ken MacLeod.
-- Bill Sloman, Nijmegen
The PPC970MP (Apple G5 dual core) was ten layers, in 2005.
compressive
=20
Nice reminder, routing area is also a function of routing layers in the "board". Which may include disconcerting properties issues with the traces.
area,=20
space=20
empirically,=20
proportional=20
honkin'=20
for=20
area.
=20
rubber-
use=20
needing=20
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