Hello,
- Is vhdl suited for designing asynchronous circuitry ? (like domino bricks).
- Is it also possible to mix "domino bricks" circuitry with "clock" circuitry ?
If not is there any other language which can do 1 or 2 ?
Bye, Skybuck.
Yes, because your 'async circuit' is nothing but gate delays. Yes, for the same reason. Yes, Verilog, others. Bye.
Read the full replyHello,
If not is there any other language which can do 1 or 2 ?
Bye, Skybuck.
On a sunny day (Mon, 19 Feb 2007 13:19:19 +0100) it happened "Skybuck Flying" wrote in :
Yes, because your 'async circuit' is nothing but gate delays.
Yes, for the same reason.
Yes, Verilog, others.
Bye.
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