Any logic-level FETs with breakdown 300V+?

that have a guaranteed Rdson of around 1ohm or less

tables. The usual ones are only rated at 10V

drive voltages at lesser current. But the

is like kicking a big oak tree.

too much money plus it would need its personal supply

Mouser has them. :)

And why can't you use a charge pump inverter source on the driving side for the gate? I've done that before using simple things like a PNP for high side to drive the gate via a charge pump inverter and common on the low side via a open collector NPN drive.

It works perfectly, since the charge pump reservoir cap has more than enough to over come the Cgs on the gate for the initial transition. You may also consider a low value R in series with gate to avoid parasitic noise, like ringing for example. Many times board design can over come this how ever, it does not hurt to through in a 1..10 R.

Or, just use a ready made gate driver chip with the same characteristics.

Well, there ain't so much space left as for a carpenter ant to squish in there ;-)

Needs a separate supply and thus even more space. But if all else fails that's what we'll have to do. On another design a month ago I did that but there I had over 200 square inches of free land. So I just stuck a claim somewhere ...

Making a low yield supply on board to drive a fet should be a trivial task, one that requires very little real-estate. The size of gate driver chips are very small these days. One could even plant a mini daughter board just in front/over the top of the FET if space is tight.

Did that the other day btw, to modify a circuit that was already in use.! Needed to enhance a analog PID board, so I etched out a mini .5" square DS board and elevated it over the main board with the connection legs...

In your case, I guess if you wanted to design this into your board you could use a header and simply make the danghter board removable.

You don't need much additional space for this :

| | | | ||-+ |||----+-----||-+ | | --- | --- ||-+ | ||-------+-----||-+ | | === GND

On a sunny day (Mon, 03 Nov 2008 13:15:58 +0100) it happened Fred Bartoli wrote in :

The charge on the capacitor is undefined if the circuit is 'on' for a long time. Even with a good capacitor, but say some humidity, it may leak away, also via the diode, the top gate voltage will slowly drop, Rds-on goes higher and higher, and BOOM.

But it is a cool solution when there is a guaranteed low activation frequency. But Joerg cannot say what it is for.... Maybe he can say what the lowest frequency is.

Jan Panteltje a écrit :

Obviously, but 'I think' Joerg stated it was for pulse operation. Anyway he'll discard the circuit if it's not suitable to it's needs.

Unfortunately I can't say but yes, like most switchers it does have to stop once in a while. But the main issue is that now we'd need two large transistors and there just ain't space for yet another DPAK size.

Thanks anyway, Fred. Very kind.

"Joerg" a écrit dans le message de news:K0GPk.6689$ snipped-for-privacy@nlpi061.nbdc.sbc.com...

Yet another DPAK? Sheesh...

FDC637AN in SuperSOT6 32mOhm @2.5V Add an SC70 diode and a 0603/0402 cap. And in case you need several it's even half an SC70 diode!

Or you have FDMA410(9A!) - FDMA420(5A) in a 2x2mm package

-- Thanks, Fred.

Yeah, possibly, but we've got some nasty peaks through there so it could easily vaporize a bond wire in those small packages.

Oh, sorry I thought you wrote:

"that have a guaranteed Rdson of around 1ohm or less at Vgs of

-- Thanks, Fred

Yes, on average. Peak losses are very brief and don't contribute much. Unless a bond wire goes ;-)

But the real problem is that we really do not have any space. Aggravated by the fact that this app requires more clearance than usual between serious voltages.

Not so sure that would be safe for the logic level fet.

The Cap can lead ahead causing the HV fet to turn on sooner than the logic fet does. HV could thus damage the logic fet before it gets down in the Ron value.

Also, you have the case where free charge could be on the gate at initial start up, because I don't see a loading R to prevent that.

Oh well, just my observations from the peanut gallery..

The HV fet source is not expected to exceed the HV fet gate voltage; the gate coupling caps are required to be >> greater than Cgs, for basic function.

RL