" I doubt that they are frivolous, but I am not sure what is behind them and who would gain from AMD going bankrupt - and, no, it's not the money as such but the loss of 'confidence' that would bring AMD down. Cui bono? And, no, it's not likely to be Intel. "
It's pretty god damn obvious. ARM ofcourse... who else ?! lol.
Bye, Skybuck.
So ARM processors can't have "cores"?
"Preferably?" Reduced from what? Two cores will always have lower performance than twice that of a single core. You make no sense, as usual.
Nope. Caches, particularly L2s, are usually not part of the core. Again, the definition depends on the microarchitect.
What does that have to do with anything?
" So ARM processors can't have "cores"? "
This is about x86/AMD64 cores.
What NVIDIA's GPU or ARM CPU calls a core is beside the topic as far as I am concerned, because these buyers are buying these AMD chips to execute X86/AMD64. So the topic has to be specified to just that, otherwise the discussion becomes way to broad and meaningless and abstract and has no practical/consumer value.
" "Preferably?" Reduced from what? Two cores will always have lower performance than twice that of a single core. You make no sense, as usual. "
You don't seem to make any sense to me... Take a core, take another core, slam it together on a single chip, done.
You have exactly the same core... use reduced transistor size/nanometer process.
And each single core may actually work faster then before.
It makes no sense to double the number of cores, if the performance is halved.
How does that create a faster chip ?!?
It doesn't, duh.
Furthermore there is little reason why there would be any performance degradation whatsoever.
Design it properly.
" Nope. Caches, particularly L2s, are usually not part of the core. "
Ok, could be my mistake... I wasn't sure about that... :)
What isn't doesn't mean it couldn't be in future ! ;)
" Again, the definition depends on the microarchitect. "
L1 caches have been part of x86 architecture cores for quite some time now.
So a consumer can expect this kind of chip/performance etc.
And x86 chip not having an L1 cache... would be pretty fraudy.
The cache is basically why Intel entered the processor bussiness.
No cache, no intel ! ;)
" What does that have to do with anything? "
It's something for the consumer to expect.
What's even more odd is that many websites never mention the L1 cache size which is highly strange/suspicious.
I think my AMD had something like L1 64 KB or maybe even L1 256 KB... not going to start CPU-z.
As far as I am concerned cache is so important it might as well be included in the process name:
AMD X2 3800+ 256 KB version ! ;)
No cache, no nothing ! ;)
Bye, Skybuck.
" If that is true then the chips are up for AMD. "
?" They should have abandoned the PC market 6 to 10 years ago and focused on mobile. "
Hind sight. Their chips too hot, bad idea.
"They also mess up the transition to 64 bit computing by introducing a 64 bit PC chip with legacy instruction set support first, "
This is what they have done correctly and intel failed at.
"where Intel had wanted to remove all that junk from the instruction set."
That would have been the end of intel lol. In a way AMD saved intel LOL.
"Actually the ARM 64 bit design is messed up too, with tons of unjustifiable SIMD instruction that will never be used (by a c compiler or human), and just waste silicon."
Android seems to need something like that to run well... so it might be an OS-necessary thing, perhaps for GUI acceleration.
"The ordinary 64 bit instruction set is actually great"
Which one, the ARM one ? ;)
" and would have made a very small and effective core on its own. "
Small sounds nice.
" AMD are due to pay back a ton of money in the next couple of years, "
Hmm, what you mean exactly ? Money from lawsuits ? ;) Loans ? Investors ?
" VW-ing isn't a good idea. "
Very wide ?
Bye, Skybuck.
So you're definitions only apply to one product? Rather pointless (but not surprising).
The definition of the word is the problem. If people can't agree on what it means, it becomes a useless word. It's up to you to understand what the speaker means. That's the whole point. If you think you got suckered, look no further than the mirror.
You're being circular. What is a core? Why does it have to be a single chip?
Also irrelevant.
Nonsense.
Of course no one said any different. You're trying to inflate a straw man.
Define "properly".
That certainly doesn't surprise anyone here.
That's up to the microarchitect. But making that a definition is absurd.
So what? No one said otherwise. They need not be part of the core, nor need they be exclusive to one fetch unit. Multi-ported L1s aren't unheard of.
WTF are you yammering on about now.
Perhaps but irrelevant.
What?!!!
Why should the consumer care? It's a microarchitectural detail.
It used to be, but apparently it's no longer important.
False, of course.
" So you're definitions only apply to one product? Rather pointless (but not surprising). "
No, it applies to the instruction set that the processors are designed for.
Why would discussing anything else be not pointless ? ;)
" The definition of the word is the problem. "
It's to late to define something to the word "core".
Core is also to abstract. If somebody or something wants to define "core" or something else... he/she is free to do so especially in light/context of something else.
Wanna call a ferrari engine a "core" fine with me.
However we are not discussing ferrari engines... we are discussing x86/amd64 engines.
"If people can't agree on what it means, it becomes a useless word."
It's an abstract word, duh.
"It's up to you to understand what the speaker means."
There is no doubt to what AMD means with "core" or anybody else pretending to sell x86/amd64 executable engines.
A core which can execute the x86/amd64 instruction set.
In that light AMD has deliver 4 cores, not 8, pretty obvious.
Hence what's next Ferrari selling engines with "virtual pistines" or whatever those things are called lol.
"That's the whole point. If you think you got suckered, look no further than the mirror."
No. The sucker is AMD... trying to sell something as 8 cores, which are obviously 4 cores.
Except AMD now calls it "MODULES" LOL.
So what's the future to bring ?
Will we now call it a MODULE from now on ?
It has lameness written all over it.
" You're being circular. What is a core? Why does it have to be a single chip? "
Because it has to be able to execute the logic it was design for.
If it cannot execute the logic it was designed for, throw it in the waste basket, it's useless.
That's basically how useless these AMD cores are for anybody trying to design an 8 CORE computer to execute 8 threads.
High chance that some of these 8 threads will stall, thus useless.
" Also irrelevant. "
Nope.
" Nonsense. "
Exactly the opposite.
" Of course no one said any different. "
You said reduced performance.
Why would two cores have reduced performance ?
"You're trying to inflate a straw man."
... please keep discussion technical.
Define "properly".
No performance degradation.
Here's a hint, don't share, duplicate everything.
" That certainly doesn't surprise anyone here. "
It will surprise you in the future when L2 cache is integrated. It may already have been. Where it is located is not the most relevant part.
The most relevant part is 4 not 8. Once it has 8 we can discuss it's location further.
The assumption for now is 8 caches will perform better than 4 caches.
Even if those 4 caches were closer to the chip... and those 8 caches were further away from the chip... the distance would not be that great... and the 8 will probably perform faster. Ha-Ha ! ;) =D
If not integrate them next time ! ;)
" That's up to the microarchitect. But making that a definition is absurd. "
No it's not... I am aware that this L2 Cache is on chip... if it were anywhere else it would not matter much and would not be called a cache but just main ram.
Here is a picture for you:
Question that remains is:
Should a core have it's own/private access to L2 cache... or should it be shared...
This is a strange question to ask... and depends more on heuristics and actually execution tendenacies and cache hit ratios and cache design.
L1 cache could hold frequent data/instructions.
L2 cache could hold less frequet data/instructions and prevent storage of frequent data/instructions which is already held by L1, thus bypassing those.
L3 cache can hold even less frequent data/instructions and so on.
L1 = 100x speed up L2 = 10x speed up L3 = 5x speed up
Maybe something like that... for actual speed ups check chip and memory specs.
" So what? No one said otherwise. They need not be part of the core, nor need they be exclusive to one fetch unit. Multi-ported L1s aren't unheard of. "
For good performance each core will need it's own L1 cache.
Anything else can be considered garbage.
" WTF are you yammering on about now. "
All intel/AMD chips include L1 cache per core, go check the specs.
It's part of what is to be considered an x86/amd64 core, what this discussion is about.
" Perhaps but irrelevant. "
No not irrelevant, spot on.
Next time AMD tries to sell a 16 core x86/AMD64 processor without L1 caches, they'll be sued again, and again, and again.
Unless they very clearly market it is: A processor without L1 caches, and therefore completely useless performance-wise lol.
" What?!!! "
Exactly like I said.
No cache, no intel.
If intel starts selling chips tomorrow without cache, it's end of bussiness for them.
" Why should the consumer care? It's a microarchitectural detail. "
No it's not a detail, it's the only reason why intel exists.
Otherwise anybody's chip would just be as good.
" It used to be, but apparently it's no longer important. "
It is important, ask NVIDIA which now introduces larger L1 caches for the GPUs to prevent bottlenecks.
" False, of course. "
Again, see recent GPU design ! ;)
No cache=might as well call it a old-fashioned GPU lol.
Bye, Skybuck =D
Well, discussing anything with you is pointless (but so is television).
Perhaps, but pointless in any case.
Exactly. So why are you whining?
So define "core". Now, get everyone, including the FTC to agree with your definition and you might have a point.
...and here we are.
Of course it is.
DIf there is now doubt, then why are you whining?
No, we've already been over this.
No, it's not at all obvious. It's not even right.
You mean intestines?
You obviously have a different dictionary than others here.
More whining about nothing.
Unlikely, unless there is good reason to do so.
...and your point is (other than the one between your shoulders, that is)?
Are you saying that AMD parts don't work? Again, why does it have to be a single chip? Why doesn't an MCM qualify?
I'd agree. I'd call it a defective part.
Of course you're wrong but that's not new either.
THere is always that chance. The more cores, the higher that chance.
What does the transistor size have to do with the microarchitecture? Of course it doesn't.
You really are a dumbshit.
You can't read but that's not surprising either.
Less than twice a single core, dummy!
You don't like facts. We get that.
Not possible. Sorry.
If they shared everything, even they wouldn't say that it had multiple of anything.
L2s are normally integrated. You've really lost it.
What "it's". I hope not.
That's certainly an uninformed assumption.
More uninformed blather.
I thought you just said it wasn't integrated. Make up your mind (impossible, I know).
It should have what the microarchitect designed it to have. He's the one paid to make such decisions.
It's a lot more than that.
Could? Well, one certainly hopes.
You really are a simpleton.
Not necessarily true at all.
I guess you're garbage.
Then what are you whining about. It's not written in stone anywhere, though. Again, multiport caches are pretty common. L1s tend to be simple but it's not written in stone.
No, this discussion is all about you whining about what you clearly don't understand.
No, irrelevant. If there were some other way to get acceptable performance it wouldn't be fraudulent at all. I bet you're one who would hang Muntz, too.
...and it'll get laughed out of court, again, and again, and...
You assume a lot.
You really are stupid.
Wrong! Intel exists to make money. If they can make money making processors without an L1, they will still exist.
Ah, so no one else can make an L1?
No, it's not important. Performance is important. Measure that, not the size of the cache. Buy the *performance* you need, not the bits you think you need. They don't matter.
\\\
broadwell is nowhere to be seen, but I see all shops here have skylakes...
Well, since sandy bridge, intel didn't step up in performance in major way but there are improvements here and there. What is interesting is hype around AMD Zen, which will supposedly bring performance on par with intel. I wish that would be success.
According to ,
10 shops in Austria have the Core-i7-5775C (Broadwell) in stock.According to
16 have the Core-i5 6500 (Skylake 3.2/3.6GHz) in stock, so yes, some Skylakes are available, but for the Core i7-6700K (4.0/4.2GHz), only one shop has it in stock (and holds on to the ones that they have by asking 40% more than you pay for the Core i7-4790K (Haswell 4.0/4.4GHz)).By contrast, 19 shops have the Core i7-4790K in stock .
So yes, Skylakes are in shops, but the scarcity of the 6700K suggests that only few of the produced Skylakes come out in that bin, while fast Haswells are not scarce. So it appears that it is easier to make fast 22nm CPUs than fast 14nm CPUs.
Me, too, but given that we hear little technical stuff about Zen makes me suspicious. When K8 came out, we heard a lot about the cool features that would give it an edge (and, as it turned out, gave it an edge: AMD64, integrated memory controller, and hypertransport); for Zen we hear no technical features. Let's hope that that's just newer, secretive marketing people, and that the Zen will be competetive.
- anton
-- M. Anton Ertl Some things have to be seen to be believed anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen http://www.complang.tuwien.ac.at/anton/home.html
But some of the Broadwells support the limited form of transactional memory, which makes it possible to greatly simplyfy the high-performance parallel algorithms. What sed to be next to impossible is now quite easy. E.g. even such a simple thing as a doubly-linked list was so hard to do properly that it earned Mr. Valois a Ph.D degree. With TSX it is a no-brainer.
Best regards, Piotr
So they have TSX working now?
How useful it is seems to be limited to the depth of the elision buffer(s). Documentation was not proliferate when I looked into it a year or so ago, and no hard numbers were given for any implementation. But as I understand it the core maintains a list of memory addresses which are modified during a transaction and detects the case where another cores access conflicts with the transaction. As buffer memory for this case must be finite it seems of use primarily in cases where modifications are made to small data structures. However, since we don't seem to know how deep the buffers are it seems reasonable to restrict the use of TSX/HLE to really simple structures. Performance could suffer otherwise.
I am currently waiting to get my hands on working hardware, preferably a laptop of some sort.
-- If the NLP should give you a headache, take two pills (at least) and do not call me in the morning.
" Now THAT one I considered to be a frivolous lawsuit. You pays your money, you takes your chances :-) Doesn't everyone who is looking for investors "
AMD basically does it again with zen, claiming 40% more instructions per clock.
What if you wait for this processor and then it turns out all to be a lie ?! Would you feel had/cheated/lied too ?! ;)
Bye, Skybuck.
Your posting is full of emotional crap.
I am not going to discuss your emotional crap any further.
Bye, Skybuck.
Well, discussing anything with you is pointless (but so is television).
Perhaps, but pointless in any case.
Exactly. So why are you whining?
So define "core". Now, get everyone, including the FTC to agree with your definition and you might have a point.
...and here we are.
Of course it is.
DIf there is now doubt, then why are you whining?
No, we've already been over this.
No, it's not at all obvious. It's not even right.
You mean intestines?
You obviously have a different dictionary than others here.
More whining about nothing.
Unlikely, unless there is good reason to do so.
...and your point is (other than the one between your shoulders, that is)?
Are you saying that AMD parts don't work? Again, why does it have to be a single chip? Why doesn't an MCM qualify?
I'd agree. I'd call it a defective part.
Of course you're wrong but that's not new either.
THere is always that chance. The more cores, the higher that chance.
What does the transistor size have to do with the microarchitecture? Of course it doesn't.
You really are a dumbshit.
You can't read but that's not surprising either.
Less than twice a single core, dummy!
You don't like facts. We get that.
Not possible. Sorry.
If they shared everything, even they wouldn't say that it had multiple of anything.
L2s are normally integrated. You've really lost it.
What "it's". I hope not.
That's certainly an uninformed assumption.
More uninformed blather.
I thought you just said it wasn't integrated. Make up your mind (impossible, I know).
It should have what the microarchitect designed it to have. He's the one paid to make such decisions.
It's a lot more than that.
Could? Well, one certainly hopes.
You really are a simpleton.
Not necessarily true at all.
I guess you're garbage.
Then what are you whining about. It's not written in stone anywhere, though. Again, multiport caches are pretty common. L1s tend to be simple but it's not written in stone.
No, this discussion is all about you whining about what you clearly don't understand.
No, irrelevant. If there were some other way to get acceptable performance it wouldn't be fraudulent at all. I bet you're one who would hang Muntz, too.
...and it'll get laughed out of court, again, and again, and...
You assume a lot.
You really are stupid.
Wrong! Intel exists to make money. If they can make money making processors without an L1, they will still exist.
Ah, so no one else can make an L1?
No, it's not important. Performance is important. Measure that, not the size of the cache. Buy the *performance* you need, not the bits you think you need. They don't matter.
\\\
NO, I'm just responding to your shit. That's all you have.
Please don't. Go away.
Only if I bought one. In the first article, it was AMD touting how great the APU was before it was even released (IIRC. I didn't reread the article) so they could get more development money from the investors. I think in the second case, it's more a case of false advertising.
-- SC Tom
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