Does anyone know the Verilog command within the Altera Quartus II IDE for forcing 2-d boolean arrays to be implemented using internal RAM hardware, rather than as linked logic elements?
Altera FPGA pseudoinstruction, RAM configuration
Mar 25, 2013
1 Replies
Write your Verilog to match the Altera ram inference template and it should be compiled into ram without needing to give the tools any extra hints. Do it right and it will also compile in other vendors' tools.
Off the top of my head:
parameter ADDR_WIDTH = whatever; parameter DATA_WIDTH = whatever;
... reg [DATA_WIDTH-1:0] ram [0:(1
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