Weird ADC block diagram: LTC2351

Some ADCs actually do the SAR conversion as the SPI data is being clocked out. So there is no actual data register.

But in this one, the s/h blocks are presumably drifting, so it makes sense to convert as fast as possible, and to always have the same timing, to have consistent drift-driven offsets. Maybe they really do the conversions when CONV rises, and stash the data in registers ASAP.

Full disclosure, I haven't read every word of the data sheet.

Don't the least promising interns write the data sheets?

onsdag den 16. september 2020 kl. 21.06.54 UTC+2 skrev Phil Hobbs:

it is confusing, as far as I can tell you can set it up for less that

6 channels and only clock 16x times the number of channels to convert those channels but you can always clock 96 times the data in the channels not setup to convert will just be old data

What I think is happening is that all six s/h units take a sample simultaneously, and during hold the six anamog signals are routed to the shared ADC, with results sored in the corresponding 14-bit registers, which are then read out serially. The next conversion cannot happen until this read-out is complete. If one chooses to ues fewer than 6 channels, this process is proportionally faster.

Joe Gwinn

I believe this device overlaps the conversions and and the readouts. But y ou can not shorten the sample time and increase the conversion rate by conv erting fewer channels. There is a minimum spec of 4 us. The entire set of selected channels are converted and saved as you read out the previous set of data. Then you read that set of converted data. So there is a latency of 4 us to get your data. Like Larkin said, it is probably converting usi ng the interface clock. They specifically say that if the number of channe ls selected is changed, the old data that hasn't been read out will remain so it can be retrieved when the selected channel count is changed back.

Funny part. If they weren't a small fortune I'd consider using them.

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  Rick C. 

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Seems to be the externally-clocked kind, but you can keep going for longer than needed (i.e., 16*N clocks for N channels, in order starting from 0), perhaps to keep the interface constant (no need for, say, address bits to select what channel to read from). Which will have savings both in logic, and the user's driver.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

I'm coming to the view that it's a normal SPI-clocked one, and that the drawing is just plain wrong. If it were internally clocked, there'd be no reason I can see for the requirement that the SPI clock start within

10 us of the CONV pulse.

We're going to try it out this afternoon and see if we can measure its droop vs. delay time.

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

You could hang a fet probe on top of the chip, maybe on a foil sticker, and see if it clocks itself at CONV time. I worked once with some people who were trying to identify counterfeit chips this way. Lots of chips leak visible signal.

I suggested that they measure wideband VCC current too.

I guess s/h droop is the bottom line. You could wait seconds, or hours.

There are some interesting DDG architectures that need fast, low droop s/h's. None work really well.

e

I don't know why you say the "drawing" is wrong. They clearly show a block "timing" that receives the SPI clock and drives the ADC. Everything I've seen in the data sheet shows the device IS clocking the ADC from the SPI cl ock. The main issue is that the data you are clocking out is not from this conversion, but from the previous conversion. That's why it has N registe rs rather than just one.

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  Rick C. 

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There's an analogue-ish 10 us maximum time delay between CONV and the first SPI clock, with a 10-us maximum clock period. So one is allowed at most a millisecond or so to finish the whole conversion/readout cycle.

We're going to try it out and see.

Could be the most promising ones. (*)

Cheers

Phil Hobbs

"Calypso and reggae are the same. A reggae band can afford better drugs is all."

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

Interesting idea--we'll try that while we're waiting.

Well, if you can guarantee a sufficient delay between acquisition and readout, you can do a pretty good job with a fast droopy one followed by a slower non-droopy one. (You knew that already.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

Been there, done that, still having PTSD.

Thanks for playing.

Cheers

Phil Hobbs

If the droop is measurable, then it might be easier to measure near the highest rated operating temperature, as of course the leakage should be much lower at room temperature.

Most of ricky's posts are variations on "I don't understand why you are so stupid."

He doesn't ever play.

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard

They seem to exist, as it is stated at the front page figure, then repeated at page 9., then mentioned in the text at page 17, then confirmed by the timing diagram at page 10.

They seem to use the CONV-centric approach, which they usually do anyway, not the SCK alone.

"The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC2351-14 until the following 96 SCK rising edges have occurred."

Combining that with the timing diagram shows that they expect 96 SCK cycles to be provided after the CONV trigger is activated, and they will not start talking to you sooner than that. So that implies that the

96-bit latch is real, as it is necessary to implement this interface.

Another question is why they would want such a twisted interface to begin with. I have no idea, but my SWAG would follow the Sleep and NAP shutdown modes, which are also controlled by CONV/SCK. Micropower delay-tolerant micropower conversions? Ask them. :)

Best regards, Piotr