AD5791

But you can power the chip from +/-16V and the LSB can be in the 25uV ballpark. The Johnson noise of 7.5nV/rtHz doesn't seem so bad then, does it?

Jeroen Belleman

That helps some. +-14v is about the limit on the references. We'd have to divide down to get our +-10v range back, and that would need some crazy stable resistors.

Looks like the other way to get the noise down would be to parallel a number of DACs. Times 8 channels! Ballpark $100 per DAC, which is actually feasible.

It will of course need crazy-low-noise hyper-stable references.

I wonder how ADI tests these parts. I can't buy a 1 PPM accurate DVM.

Its quoted rise time is 1us, corresponding to a 3 dB bandwidth of about 350 kHz, or 550 kHz noise bandwidth.

With 7.5 nV 1-Hz noise, the total RMS noise should be about 5.6 uV, just about half a LSB at 10V FS.

Not that shabby.

Cheers

Phil Hobbs

Never mind. The 1 us is the settling time, so the BW is wider than 350 kHz.

Cheers

Phil Hobbs

Three DACs in parallel with +-16 refs, divided down to +-10, pencils out around 3.2 nv/rthz.

I'm going to need a very good preamp to measure the noise, something below 1 nv/rthz. Any ideas?

;)

I believe you may have got one in your stocking in January.

(For others: we sell a nice 20-MHz AC-coupled preamp for noise measurements, the LA-20 Lab Amplifier. Works great, and is cheap like borscht.)

Cheers

Phil Hobbs

You can't use +-16 references, there's a 2.5V minimum headroom requirement (datasheet page 4). The part is tested and guaranteed with +-10V references; it's _possible_ the nonlinearity will be a little worse if you increase to, say, +-13.5V refs. This is a consequence of the design internals. I don't know if this was ever characterized, you'd probably have to check it yourself.

You asked about testing. I don't know how this specific part is tested, but in general there are (at least) a couple of ways.

Many automatic testers have a super DVM available as a system resource, often an HP3458A. This works well but is slow, hence is an expensive solution, i.e. it adds a lot of test time (cost).

Testers also often have a super-precision system DAC against which you can make differential measurements. With an in-amp gaining up the difference between the system DAC and the DUT (Device Under Test) by something like x100 you could use the system's fast ADC - 12 bits might even be enough. There might need to be some averaging involved. Even with waiting for the in-amp to settle this may still be easier and faster than the system DVM.

Either way, testing to 20 bits takes time, and time costs money.

Thermocouple effects can become an issue in testing something like this. One of the first parts I designed at ADI was a very linear custom VFC with very low offset and offset drift specs. I also designed and built the trim and test fixtures and needed to use high-purity copper wire and Cd-Sn solder as the part dissipated a lot of power (it was a chip-and-wire hybrid full of bipolar stuff - this was the 1980s, before there was precision analog CMOS). It's probably a lesser issue for AD5791 as the power dissipation is much lower than my part had. Probably just the Cd-Sn solder would have sufficed as it had 1/10 the thermocouple effect against copper compared with Pd-Sn solder, but the fixtures were one-offs so I went al -in.

I think I still have that roll of solder and the special flux. Now it's hazmat.

Yes, I forgot somehow. Thanks.

We'll likely need another, if we go ahead with this project, and I'll have the customer buy some too.

In fact it needs a stable thin-film array. Provided the thin-film resistors are on a common substrate, the divide ratio can be quite a bit more stable than the individual resistances which are at the same temperature and made of metal despoited at the same time.

Very stable four terminal references can be bought - they aren't cheap but there's nothing crazy about the prices or availability. You do have to be careful of voltage drops in the relevant printed circuit traces - I once had to fix a circuit where the voltage reference was grounded at the wrong end of trace carrying the return current from a big EPROM.

The quick fix was soldering a chunk of copper wire onto the track, but changing the layout to something closer to star grounding was the long term solution.

Not a enough money? No access to liquid helium? NIST seems to have managed it in 1984.

Sorry, right, the refs could be 14, to reduce the Johnson noise by

The super DVMs don't usually offer a scanner option, so we'd probably build a test box with an 8 or 9-channel relay scanner for the DVM and a super-low noise AC-coupled amp for the noise measurements.

We use some cute little DPDT telecom relays for stuff like this, latching relays to reduce coil-heating thermoelectrics. We could even gap-pad the tester PCB to a big aluminum plate to make it isothermal, although a few layers of 2oz copper would do that pretty well.

Test speed wouldn't be a big deal. Overnight test and cal would be OK. We're not making ICs!

That DAC is astounding, which makes it hard to test.

Aren't 6.5-digit DMMs exactly 1PPM?

Joe Gwinn

I think the best I've seen is something like 4 PPM. For north of $14K.

LA22

It might be easier to buy a 1ppm voltage reference and calibrate against that.

.

For a product instance:

.

Joe Gwinn

Or if you're short of funds but feeling lucky:

Nice part but costs way too much for any products we make.

boB

What do you make?

We live on the lunatic fringe of electronics, things that are really hard to do, things with extreme exponents. It makes money because it has little competition, but the money is a side effect. I do it because it's fun.

There must be something cool that we can do with a 1 PPM accurate DAC.

TI has a 20-bit delta-sigma DAC that's about $12, but it's only linear to 15 PPM. I don't understand how a d-s DAC or ADC can even be that good. It would seem to need femtosecond edge accuracies inside.

I expect that the deterministic part of the jitter gets pushed out to high frequency by the noise shaping.

Random jitter you'd have to deal with by averaging.

Cheers

Phil Hobbs

I was thinking about rise/fall time asymmetry, changing average values as duty cycles squirm all over the place.