100mV DC supply

-----------------

ourcing up to ~50mA but will typically see high impedance. Easily available I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.

8V using a buck converter then follow it up with a 1.0V precision shunt (AD R510 or other) followed by a 9:1 precision resistor divider. Buffer the 100 mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly follo wed with a BJT?

/- 3mV should be good enough. The environment the board will reside in is ~

25C +/- 5deg. The output voltage must not drift above ~130mV to prevent cau sing issues in the test chamber.

= 1kHz) and multiplied by 10x before being sampled. The low pass filter frequency is chosen to preserve rise times in the ~500uS range.

pm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best pr actice shielding techniques to mitigate induced noise.

lar to this before so I'm interested in hearing about other possible topolo gies that can meet the requirements or how others would approach the proble m. The solution will be put onto a pcb as part of a larger circuit so i can not use a benchtop supply.

** Using the KISS principle, all you need is a 5V, 1Amp TO220 reg IC and 3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types.

The 120ohm & 82ohm go in parallel to make 48.7ohms, then 1ohm in series acr oss 5V.

This makes a 1:49.7 divider so you get 100mV with a 1 ohm source impedance and a SCC of 100mA.

A small cap is also needed across the output of the reg IC for stability.

.... Phil

ourcing up to ~50mA but will typically see high impedance. Easily available I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.

8V using a buck converter then follow it up with a 1.0V precision shunt (AD R510 or other) followed by a 9:1 precision resistor divider. Buffer the 100 mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly follo wed with a BJT?

/- 3mV should be good enough. The environment the board will reside in is ~

25C +/- 5deg. The output voltage must not drift above ~130mV to prevent cau sing issues in the test chamber.

= 1kHz) and multiplied by 10x before being sampled. The low pass filter frequency is chosen to preserve rise times in the ~500uS range.

pm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best pr actice shielding techniques to mitigate induced noise.

lar to this before so I'm interested in hearing about other possible topolo gies that can meet the requirements or how others would approach the proble m. The solution will be put onto a pcb as part of a larger circuit so i can not use a benchtop supply.

The LM10 give you a 200mV reference voltage output which you could divde to exactly 100mV with 25-turn trim-pot. The op-amp part of the device could t hen buffer that voltage. You might have to load the output with a resistor ground, but the data sheet spells it all out.

--
Bill Sloman, Sydney

Yep, that's good for power efficiency. At 50 mA, that 1.8V won't take more than a tenth watt, though; what kind of buck converter is really designed for such a low load? There's probably other low voltage requirements you can combine

For 2 mV, your reference voltage requirement is a problem. A good low-voltage LDO at 0.8V output, with a 7:1 divider string (14 ohm pullup,2 ohm pulldown) has the right voltage, and only 2 ohms impedance (so your 50 mA current draws it down, but doesn't burn anything up). Would that work for you?

ourcing up to ~50mA but will typically see high impedance. Easily available I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.

8V using a buck converter then follow it up with a 1.0V precision shunt (AD R510 or other) followed by a 9:1 precision resistor divider. Buffer the 100 mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly follo wed with a BJT?

/- 3mV should be good enough. The environment the board will reside in is ~

25C +/- 5deg. The output voltage must not drift above ~130mV to prevent cau sing issues in the test chamber.

= 1kHz) and multiplied by 10x before being sampled. The low pass filter frequency is chosen to preserve rise times in the ~500uS range.

pm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best pr actice shielding techniques to mitigate induced noise.

lar to this before so I'm interested in hearing about other possible topolo gies that can meet the requirements or how others would approach the proble m. The solution will be put onto a pcb as part of a larger circuit so i can not use a benchtop supply.

Once you have +1.8V, why not something like this?

(view in Courier font) +1.8V Vref >---. -+- | | [R1] [R4] 20 | 100mV |\ | +----------|+\ |/ Q1 | | >---[R3]----| [R2] .---|-/ |>. | | |/ | === | | '--------------------+-----> Vout = +100mV | [1k] R5 | ===

Vout is a precision, low-impedance output. R4 provides short-circuit protection. R5 provides an optional minimum load.

Cheers, James Arthur

sourcing up to ~50mA but will typically see high impedance. Easily availab le I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~

1.8V using a buck converter then follow it up with a 1.0V precision shunt ( ADR510 or other) followed by a 9:1 precision resistor divider. Buffer the 1 00mV output by a low noise single supply op-amp such as ltc1014. Although i t looks like ltc1014 won't be able to source enough current so possibly fol lowed with a BJT? +/- 3mV should be good enough. The environment the board will reside in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to prevent c ausing issues in the test chamber.

ve = 1kHz) and multiplied by 10x before being sampled. The low pass filte r frequency is chosen to preserve rise times in the ~500uS range.

0ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best practice shielding techniques to mitigate induced noise.

milar to this before so I'm interested in hearing about other possible topo logies that can meet the requirements or how others would approach the prob lem. The solution will be put onto a pcb as part of a larger circuit so i c annot use a benchtop supply.

3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types.

cross 5V.

e and a SCC of 100mA.

Right, that's what I'd try. If you need a lower source impedance maybe buffer with an opamp. (Is there some dip opamp that does ~100mA besides the TCA0372?.. too lazy to troll Digikey.)

George H.

of sourcing up to ~50mA but will typically see high impedance. Easily avail able I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.8V using a buck converter then follow it up with a 1.0V precision shunt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffer the 100mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly f ollowed with a BJT?

nd +/- 3mV should be good enough. The environment the board will reside in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to prevent causing issues in the test chamber.

tive = 1kHz) and multiplied by 10x before being sampled. The low pass fil ter frequency is chosen to preserve rise times in the ~500uS range.

(70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from th e 5 foot run of cable to the test chamber and back and am interested in bes t practice shielding techniques to mitigate induced noise.

similar to this before so I'm interested in hearing about other possible to pologies that can meet the requirements or how others would approach the pr oblem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

d 3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types.

across 5V.

nce and a SCC of 100mA.

y.

I interpret the OP as needing 100mV and holding +/-3mV for currents of

0

The best references are mostly in the 2.5 to 10 volt range, so you could use one of them and divide down. There's an LM4040 at 2.5 volts,

0.1%, fairly cheap. The ADR refs from ADI are amazing, tempcos down to 3 PPM, for a few dollars, so the ADR510 should be OK.

You might consider a 4-wire remote sense configuration to zap the error of 50 mA in the lead wires.

Susumu makes cheap 0.1% thin-film resistors with tempcos typically below 10 PPM.

2% tolerance should be easy, unless you have ground-loop issues. You could start with an isolated DC-DC converter.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Looks like a TL431...

sourcing up to ~50mA but will typically see high impedance. Easily availabl e I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1 .8V using a buck converter then follow it up with a 1.0V precision shunt (A DR510 or other) followed by a 9:1 precision resistor divider. Buffer the 10

0mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly foll owed with a BJT? +/- 3mV should be good enough. The environment the board will reside in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to prevent ca using issues in the test chamber.

e = 1kHz) and multiplied by 10x before being sampled. The low pass filter frequency is chosen to preserve rise times in the ~500uS range.

ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best p ractice shielding techniques to mitigate induced noise.

ilar to this before so I'm interested in hearing about other possible topol ogies that can meet the requirements or how others would approach the probl em. The solution will be put onto a pcb as part of a larger circuit so i ca nnot use a benchtop supply.

He only needs +/- 3% over 10oC, so that part should be pretty straight-forward. Even the humble LMV431 comes in 0.5%, jelly-bean from Digikey.

Cheers, James Arthur

of sourcing up to ~50mA but will typically see high impedance. Easily avail able I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.8V using a buck converter then follow it up with a 1.0V precision shunt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffer the 100mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly f ollowed with a BJT?

nd +/- 3mV should be good enough. The environment the board will reside in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to prevent causing issues in the test chamber.

tive = 1kHz) and multiplied by 10x before being sampled. The low pass fil ter frequency is chosen to preserve rise times in the ~500uS range.

(70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from th e 5 foot run of cable to the test chamber and back and am interested in bes t practice shielding techniques to mitigate induced noise.

similar to this before so I'm interested in hearing about other possible to pologies that can meet the requirements or how others would approach the pr oblem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

comes close.

The OP talks about a load that can source 50mA at +100mV, which seems to im ply that he wants an op amp that can sink 50mA from +100mV into the negativ e rail (ground here) which is asking a bit much, even from the MC33201.

You might be able to do it with an N-channel MOSFet - most op amps could dr ive a big-enough MOSFET gate hard enough to let the MOSFet sink 50mA to gro und from +100mV. The capacitative load would make the circuit a pain to fre quency compensate, and you'd probably have to dump in a few extra mA from t he positve rail to keep everything tidy when the load was high impedance.

The rest of thread makes it sounds as if he wants to deliver 50mA into the load at +100mV, which is much less difficult.

--
Bill Sloman, Sydney

f sourcing up to ~50mA but will typically see high impedance. Easily availa ble I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.8V using a buck converter then follow it up with a 1.0V precision shunt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffer the

100mV output by a low noise single supply op-amp such as ltc1014. Although it looks like ltc1014 won't be able to source enough current so possibly fo llowed with a BJT?

d +/- 3mV should be good enough. The environment the board will reside in i s ~25C +/- 5deg. The output voltage must not drift above ~130mV to prevent causing issues in the test chamber.

ive = 1kHz) and multiplied by 10x before being sampled. The low pass filt er frequency is chosen to preserve rise times in the ~500uS range.

70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in best practice shielding techniques to mitigate induced noise.

imilar to this before so I'm interested in hearing about other possible top ologies that can meet the requirements or how others would approach the pro blem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

The TL431 is shunt, though, sucking maximum current all the time, and outpu ts

2.5V where the OP requested 100mV.

Cheers, James Arthur

e of sourcing up to ~50mA but will typically see high impedance. Easily ava ilable I have a clean 24V source and 208VAC. My intent is to drop from 24V to ~1.8V using a buck converter then follow it up with a 1.0V precision shu nt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffer t he 100mV output by a low noise single supply op-amp such as ltc1014. Althou gh it looks like ltc1014 won't be able to source enough current so possibly followed with a BJT?

and +/- 3mV should be good enough. The environment the board will reside i n is ~25C +/- 5deg. The output voltage must not drift above ~130mV to preve nt causing issues in the test chamber.

active = 1kHz) and multiplied by 10x before being sampled. The low pass f ilter frequency is chosen to preserve rise times in the ~500uS range.

t (70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but from the 5 foot run of cable to the test chamber and back and am interested in b est practice shielding techniques to mitigate induced noise.

g similar to this before so I'm interested in hearing about other possible topologies that can meet the requirements or how others would approach the problem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

and 3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types.

es across 5V.

dance and a SCC of 100mA.

ity.

Sure... you know my opamp idea is probably not so good. I used an opamp as a voltage reference in a circuit and then found when I hung a bunch of bypass caps on the output... It sang for me. :^)

Your circuit with transistor would be better.

George H.

Some opamps, especially RRO types, are c-load stable.

Almost any opamp is c-load stable with enough C!

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

ote:

able of sourcing up to ~50mA but will typically see high impedance. Easily available I have a clean 24V source and 208VAC. My intent is to drop from 2

4V to ~1.8V using a buck converter then follow it up with a 1.0V precision shunt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffe r the 100mV output by a low noise single supply op-amp such as ltc1014. Alt hough it looks like ltc1014 won't be able to source enough current so possi bly followed with a BJT?

ion and +/- 3mV should be good enough. The environment the board will resid e in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to pr event causing issues in the test chamber.

le active = 1kHz) and multiplied by 10x before being sampled. The low pas s filter frequency is chosen to preserve rise times in the ~500uS range.

hunt (70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but fr om the 5 foot run of cable to the test chamber and back and am interested i n best practice shielding techniques to mitigate induced noise.

hing similar to this before so I'm interested in hearing about other possib le topologies that can meet the requirements or how others would approach t he problem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

IC and 3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types .

eries across 5V.

mpedance and a SCC of 100mA.

bility.

mA

I once put a 100,000uF low e.s.r. capacitor on the output of a SMPS. It cleaned up the load-step response nicely.

Cheers, James Arthur

Thank you everyone for the input, very much appreciated.

I am not overly concerned about efficiency in this design so dividing down a linear regulator does seem like a much easier approach.

James: Thank you for the hint to view in courier font, i had wondered how the hell everyone on here was parsing this style of schematic. I think this would work well

Bill: I definitely misspoke in saying that I need a load which can source 50mA, it is the simpler issue of driving a resistive load with +100mV and having it draw up to 50mA.

John: Thank you for the input. Adding two extra wires for for a kelvin arrangement doesn't complicate matters too much so I'll throw together two test setups and see how much of a difference it makes.

My plan at this point is to build several different topologies and compare. Probably overkill but I get to build up a few different quick test beds and I'm sure will learn more in the process.

Mark

ote:

able of sourcing up to ~50mA but will typically see high impedance. Easily available I have a clean 24V source and 208VAC. My intent is to drop from 2

4V to ~1.8V using a buck converter then follow it up with a 1.0V precision shunt (ADR510 or other) followed by a 9:1 precision resistor divider. Buffe r the 100mV output by a low noise single supply op-amp such as ltc1014. Alt hough it looks like ltc1014 won't be able to source enough current so possi bly followed with a BJT?

ion and +/- 3mV should be good enough. The environment the board will resid e in is ~25C +/- 5deg. The output voltage must not drift above ~130mV to pr event causing issues in the test chamber.

le active = 1kHz) and multiplied by 10x before being sampled. The low pas s filter frequency is chosen to preserve rise times in the ~500uS range.

hunt (70ppm/C), the resistor divider (25ppm/C), or the Op-Amp ~160uV but fr om the 5 foot run of cable to the test chamber and back and am interested i n best practice shielding techniques to mitigate induced noise.

hing similar to this before so I'm interested in hearing about other possib le topologies that can meet the requirements or how others would approach t he problem. The solution will be put onto a pcb as part of a larger circuit so i cannot use a benchtop supply.

IC and 3 resistors. The resistors are 120ohm, 82ohm and 1ohm - all 1% types .

eries across 5V.

mpedance and a SCC of 100mA.

bility.

mA

Huh, OK, I didn't know that. Too late now. (I think I had a dual opamp, so I inverted twice and rolled of the inverters with big C's.)

George h.

Not to completely derail all the helpful discussion but google groups seems like a horrible way to view these topics. I assume most people use a usenet reader of some kind?

Not to completely derail the topic but it sure seems like using google groups to view these threads is a horrible way to go about it. I assume most people use a usenet client of some kind?