a very tricky layout topology

If the power and ground layers are well bypassed together, there is no difference. AC doesn't care what some section of copper is biased at, only what its relation is to the signal source. And if the source is a balanced pair, well then there's no unbalanced current to even worry about, you can go ahead and run it over any traces, as long as there's a more or less solid copper layer under them to maintain stripline impedances.

If you have a jungle of traces and voltages (that aren't all so well bypassed) then you may need to consider such layout.

If the connectors are very near the controller chip (under two inches or so), you don't even need controlled trace impedance or coupled differential runs. You'll have as much error in the connectors and cables as in the same length of PCB.

Tim

-- Deep Friar: a very philosophical monk. Website:

The signals on the traces can't tell what the DC voltage of the adjacent plane is. We run fast signals against ground and power planes all the time. We recently did an 8-layer board with 8-lane PCI Express, with the topside diff pairs referenced to layer 2 (+3.3v plane) and bottom pairs against layer 7 (+1.2 volts), with some on both sides, through vias. Works great.

A good stackup for a 4-layer board is something like 20/12/20 mil dielectrics, which will come out to around 0.062 finished. The power and ground planes are close, lots of plane capacitance. Sprinkle 0.33 uF bypass caps here and there, not too many.

What's your board going to do?

Well, why is the power plane NOT acting like a ground plane?

Oh.. you ruined it all; my answer was to make him think - and you had to go and ruin it by TELLING him almost everything.

because the pwr plane is not continuous. I make two positive layers. There are 5+ different rails. +12, +5, +3.3VA, +3.3VD, +2.5...

I agree with the 2 inch but pcb recommendation says: control within 2 inch and make serpentine to minimize delay. free hanging wire also works some times.

This is a power board. 10in x 5in. To minimize the forced cooling I make a lot of pcb heatsink and soldered heatsink everywhere. This board carried a lot of current (5A/3.3V, 5A/5V etc). a 37Wh battery will power a nominal power of 26 Watt and peak power of 30+ Watt or min power of 5watt.

Thanks for the FPGA BOARD. I have another question: why not cutout underneath the CONN to the left on the picture? the shielding won't help coupling from the wire???

If you split the power layer into a bunch of different pours, and keep the gap between the pours small, it won't affect the propagation of adjacent signal pairs. Supose the dielectric is 20 mils thick and the gap between two pours is 8 mils. The signal pair will barely see the gap. If you TDR'd the differential impedance, I don't think you could even resolve the plane gaps.

I'd strongly advise against messing with the ground plane.

The PCIe spec requires the two traces of a pair to be equal length to

The pic I posted runs PCIe gen1 at 2.5 gbps per lane. That's five times faster than USB 2.0. Don't worry about it too much; any reasonable shot at impedance and length matching will work fine.

om

er

I doubt to put too close will make coupling tween two power partitioning??? think about one 5V rail is switching and the other 3.3V is for analog use. The 5V switching noise will couple into the 3.3V partitioning because the gap between 5V plane and 3.3V plane is too close.

maybe I am wrong.

hnology.com=A0 jlarkin at highlandtechnology dot com

You are worrying about it too much. Bypass the planes reasonably and pour-pour coupling, and USB signal integrity, will be OK.

Switcher noise will get into analog stuff through ground loops, not capacitive coupling between power pours. So don't chop up the ground layer, and keep switcher currents localized as much as you can.

ttom

ayer

I agree with John Larkin - the capacitance between adjacent ground planes is small (if not so small that you couldn't measure it on a bare board - I'd guess of the order of 10pF) and the capacitance to the ground plane will swamp it. If you wanted to be really obsessive you could put a grounded shielding trace between the power planes - with regular vias down to the ground plane - which would dramatically reduce any capacitative coupling, but it would almost certainly be total over-kill.

-- Bill Sloman, Nijmegen

And I'll second that, as usual :-)

If by "switching" you mean turning the 5V on and off in a very fast way then this is not a good substitute for a ground plane. Mainly because USB is unfornately not a 100% differential bus. If you meant that as "coming from a switch-mode converter" then I am with John, just bypass it well and life is good.