7805 failure mode

As long as you are very confident about your loop and nobody re-spins the board without a brief bypass capacitance review. Designing a loop for an LDO feels like walking on egg shells, almost like PID tuning where after numerous Ziegler-Nichols iterations it suddenly works but nobody is 100% sure why.

Can't you design the flyback so it generates a very precise 3.3V and the

If you make your own ldo from an opamp and a power fet, the loop dynamics is easy... especially so if you can use an n-channel fet as a follower.

unreg in | | | opamp | ref--------- + d out--------+------Rg--------g nmos fet +----- - | s | Ccomp | | | | | Rcomp | | | | +--------------------+------Rs---------+------- out | | Cout | | gnd

It's the damned LDO chips, with their pnp output stages and mysterious compensations, that are dangerous.

I need +12 min for headroom to make +-10.24 volt outputs, so we'll design for maybe +13 nom, so we never dip below 12. That can put the

Feedback from the 3.3 would require the annoying optoisolated error feedback thing, with its own problems. And still the possibility of frying the logic if the loop ever gets unhappy for some reason. We're getting our feedback from an aux winding referenced to the input side.

John

Ok, that ought to be stable. It slipped my mind that you have the luxury of higher rails for the opamp so there is always headroom to drive the gate.

$90? Ouch!

Hmm, I never had problems with the opto thing. Except getting the necessary cert paperwork for medical and in the beginning the purchasing folks had a hard time to ensure a steady supply of the wide-body SMT versions. Mostly because semi mfgs are sold and acquired all the time.

The aux winding method will be tolerance prone, there I understand your need for post-regulation.

The slickest one was this: A carrier fed back via the switcher's transformer. This was driven by the usual TLV431 deal on the secondary side and the carrier regulated the switcher duty cycle.

An LDO with an NFET follower? Maybe LDO means something else to you, but generally makes no sense unless you boost the gate drive...

Okay, you're getting there, but that is such an ugly drawing.

LOL

John has 12V on the opamps but only needs 3.3V out the source of the FET. Plenty of gate drive, I'd say. Of course, whenever you and I happen upon such a situation Murphy's law says there is not 12V rail.

Looks like late-renaissance style.

As has been mentioned elsewhere, a couple of times, the opamp is powered by +12, so the fet can be driven to milliohms of Rds-on when needed.

You never design electronics, so you laugh.

John

The +12 and +3.8 are coming off a common flyback transformer. If either fails, the product doesn't work, so they may as well fail together.

It's the idea that counts. Fred doesn't have ideas, only criticism of ideas. Interesting, no?

John

Yes, but that's quite an unusual case and it's under your control. Most of the time I do not have anything but the one voltage that needs to be regulated down. Of course, one could still use an inverter to create a higher voltage just for the driver.

I'd still use an opto feedback to generate a stable 3.3V out of the flyback ;-)