74HCU04 LC Osc

The LTspice file you posted had 4.8uH. You have not mentioned the inductor or corrected the value until now. Are we supposed to read your mind to update our information?

A number of people including myself have spent time looking for that information without any success. You could have posted this information much sooner and saved us the wasted time and effort.

The coil is bad. Maybe a shorted turn. Toss it and get another coil. You can even wind your own. That way you will know the Q. Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Simulated with a real 74HCU04 model (from my ON-Semi design files), I get fosc = 5.14932MHz

I assumed RL = 1.569 ohms (QL = 100 @ 5.2MHz)

...Jim Thompson

Solved it. It was the ceramic capacitors. I've just tried two Lemco silver micas from my junk box, and it's working like the simulation.

Hello Mike,

Yes, I was just interested in doing the algebra, which does show that there is a small capacitive element, usually insignificant when Q is above 10. In your example above, Z12 = 1/R*(w.C1)^2 - j/(w.C1) gives the input impedance as a 1109 ohm resistor in series with 431pF, where 431pF is about 74 ohms at 5MHz.

Yes. Being able to calc the input-R quickly is useful. For example, that 1109 input resistance should also have shown about a 1/4 attenuation of the input signal.

Knowing that (more or less) the same value of current has to flow in both capacitors is also useful because it is then easy to see that Vout = -Vin*C1/C2.

I like LTspice and use it more often than breadboarding these days, but still like to do some of the algebra and get a mental handle on things.

Now then Mike.... why should C1=C2? What are the design choices that determine the ratio of C1 and C2?

You don't want a voltage step-up between gate output and input, because the input voltage would swing outside the power rails. Going the other way (step-down) would increase loading on the tuned circuit due to the output series resistor.

What type of capacitor is:

1. physically small
2. available leaded (i.e. not SMT)
3. suitable for use in high-Q tuned circuits?

Where can I find LTSpice models for the NMOS and PMOS transistors in

TIA Andrew.

You generally can't, they're proprietary. I have them, because I design chips for a living, but I can't share them.

...Jim Thompson

Andrew Holme wrote: (snip)

(snip)

Most available would probably be NP0 or C0G type ceramic. If you can find a negative tempco ceramic, they might partially compensate the positive tempco of the inductor, and force a more temperature stable frequency. But they are a lot less available than the more stable, C0G and NP0 types. Other rather stable and low loss available types would be polystyrene, polypropylene and possibly mica. But they will be larger and probably more costly.

You might join the Yahoo LTspice group and ask then many knowledgeable people, there.

I use a simplified model based on the tanh function and some capacitances and an output resistance. It simulates fast, but I can't vouch for its accuracy on the details.

Hi Tony,

That is funny. The phase angle goes negative below resonance and hits a peak of about -8 degrees, then it returns slowly to zero.

The phase plot shows capacitive reactance as a positive phase angle, not negative. So something is screwy somewhere.

That tallies with the loss through the network at about -12.04 dB.

That is Ok as far as it goes, but things rapidly get a lot more complicated when you include the stray capacitance across the inductor. Just a few pf makes a drastic change in the network.

It's like the old days when we all used slide rules. When HP came up with the 35, most people eventually threw their slide rules away and never looked back.

Mike Englehart has done the same thing with LTspice. It is fast and takes little space. The files are short enough to post in a newsgroup, so we don't need abse anymore where the posts fall off the newsreader in a few days. And the few people who were good at ascii art, including yourself, now have a much better method of conveying circuit ideas.

Here's some thoughts. When the output of the inverter is in full saturation, the output square wave is between VCC and ground. The fundamental sine wave amplitude is larger than the square wave, I forget how much at the moment, but this fixes the input level to the tank.

We have not included the stray capacitance across the tank inductor, which will complicate things, but the loss through the tank increases as the Q decreases. With commercial inductors having a Q of around 30, the loss is about 12dB as you point out earlier. With equal capacitor values, this means the output voltage of the pi network will be 1/4 of the input signal available from the inverter.

We need to arrange the capacitor ratio to give the largest signal to the input of the inverter to keep the inverter in full saturation.

My guess is with a fixed input signal and inductor Q, changing the cap ratio to increase the output voltage will also increase the attenuation at the input to the pi network. So we may not gain much with a different cap ratio.

This is easy to check with LTspice. I'll give it a try later when I have some time. Meanwhile, can you tell why your calculation gives a capacitive input impedance, and LTspice shows an inductive phase angle below resonance?

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

I was way off. Making the input cap 5 times larger than the output cap increased the loss about 3dB, but it also increased the Q dramatically.

Going the other way, with the output cap five times larger than the input cap, the loss fell to about 6dB, but the Q plummeted. So we have to include Q as part of the tradeoff.

I also added calculations for the inductor stray capacitance in Mercury and included it in the LTspice analysis.

My earlier observations about things going crazy were somewhat exaggerated. The stray capacitance merely adds in parallel with the series value of C1||C2 and lowers the resonant frequency.

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Ask and ye shall receive.

Although it looks as if we may soon be out of a job:)

As reported in the Yahoo LTspice forum, a brilliant phd has written an optimizer for a number of SPICE programs, including LTspice.

The program appears to be quite small, and at least one person is having success using it, although he reports some difficulties with the variable LTspice output format.

The original announcement is at

The examples include a CMOS inverter optimized for ~800MHz. This might be comparable to a current Fairchild product, and might be a good starting point for a working SPICE model of the 74U04. Other examples include a CMOS op amp and an efficient RF output stage. (There are more examples, but I just scanned the docs briefly and can't remember them all.)

For someone who may not wish to log on the Yahoo LTspice forum, the program is available at

If this pans out, it would be a very important enhancement to LTspice.

Since the source code is available, it appears that any problems encountered in using it will eventually be overcome.

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Hello Mike,

If I include the R-value, your 5MHz parallel tuned circuit circuit becomes resistive at 4.9975MHz.

But RUN your circuit and plot V(vout)+V(vin). Now expand the scale and see exactly where the *overall* phase shift crosses zero. It's at 5.0022MHz..... and if the amplifier had zero phase shift this is where it would oscillate.

Now add to the plot V(vcap). At 5.0022MHz it's phase shift is about -3.8 degrees. Now that implies that at the frequency of oscillation the input impedance of the pi-network is not purely resistive.

For the R+L+C1 branch the phase angle between the voltage across it and the current drawn is Tan(theta) = (XC1-XL)/R. Tan(theta) can only be -90 degrees if R is zero.

For 431.1pF+4.7uH+4R92, at 5.0022MHz, Tan(theta) = 86.19 deg.

A little nit-picky for a Q of 30 or over, but it is there nonetheless.

It's not Q as such Mike, it comes back to that R+L+C1 branch. That also has a resonant frequency, the usual Fo= 1/2.pi.root(LC1). The phase shift, (given by Tan(theta) in my previous post), is moving fastest at that Fo, getting quite soggy out beyond about 1.03*Fo.

So it seems desirable that Fo of the R+L+C1 branch has to be as close as possible to the frequency of oscillation. This implies that C1 should be much lower than C2.

Hi Tony,

I combined your two posts to make one reply.

That was my question. How can it be -3.8 degrees? That implies some inductive reactance. But your equation says the input looks like a resistor in series with a capacitor. This produces a leading phase shift, which is positive on the graph.

Just curious to track down this anomaly.

Hi Tony,

The Q definitely changes when you change the cap ratio. You can see the bandwidth change.

The 3.3k is in parallel with a portion of the tank. Making the input cap (C1) much larger means the 3.3k is across a smaller portion of the tank, so it presents less of a load. The same effect occurs when changing the cap ratio in a Colpitts.

The tank Q increases, which increases the output voltage. This is why making C1 five times larger than C2 only decreases the output voltage by about 3dB.

Conversely, making C2 five times larger than C1 means the 3.3k is across a larger portion of the tank, and the Q drops. So even though we are increasing the voltage at the input to the tank, the output voltage only goes up by about 6dB.

We are limited by the signal required to drive the inverter.

So, with a fixed VCC, inverter gain, and inductor Q, we can optimize the input resistor and cap ratio to give the highest tank Q.

Now the question is, can you work the optimization into your equations, or does that take an optimizer program like ASCO?

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Since CMOS is so ratiometric, optimizing an inverter is rather trivial...

Size ratio of P:N is set by making the threshold at mid-supply.

Then you scale them both together to "optimize" speed... really a tradeoff between power consumption you can tolerate versus speed (gm/C is constant).

...Jim Thompson

I need do do more thinking to see where that anomally is.

Agreed Mike.

Assume R1 is the (3k3) feed resistor, R2 is the inductor's (4R92) resistor, and we are looking at the overall network at the frequency specified by w.L = (1/w.C1) + (1/w.C2). That frequency is *very* close to when the overall phase shift is the required 180 degrees, at 5.002MHz.

Assume also that the Cin/Cout ratio is K.

The overall Gain peaks when K^2 = 1 + [(w.L)^2]/R1.R2.

For your LTspice circuit K = 1 gives an overall Gain of 0.2513. The formula gives K = 1.53, giving a soft peak in the Gain of 0.265. ( Cin/Cout= 545.34/356.43pF.) I also tried to see whether K had any effect on the rate of change of phase shift at the 180-degree point. I could not complete the algebra, so had to resort to what-if's in LTspice.

When K=1 it is 105 Degrees/MHz, reducing for K < 1, but reaching a soft peak of about 121.8 Deg/Mhz when K= 2.5.

Note that over K values of 5 to 1/5 the 180 degree frequency point remained in the 5.001-5.002 MHz range.

Oh hell.... I forgot the Gain formula.

Overall Gain = (M*K)/[N*(R1 + M/N)].

Where M = [(w.L)^2]/R1 or M = 1/[(w.Ct)^2)*R1], Ct = 1/C1 + 1/C2 and where N = (1+K)^2.

If I've written those down right it might be interesting to see if the Gain sum is in the ball park for crystals.

Hi Tony,

Tony Williams wrote:

Please let me know your results!

Interesting. How did you arrive at that?

Ha! I was hoping you would be headed in that direction:)

Tony, I was looking at using the input resistor, R1, plus the cap ratio C1/C2, to optimize the performance of the tank to meet some desired set of parameters.

For example, dropping R1 to 750 ohms and using a K of 5 gives a loss through the tank of only 3dB, but shows minimum drop in the Q from 30 to 25.9. (I'm attaching the ASC and PLT files that show this.)

Such a low tank loss would give a high input voltage swing to the inverter, which might be useful in low phase noise oscillators, or working at sub-1V VCC.

Problems like this might be perfect for an equation solver such as Roger Schlafley's Mercury. This is a great program for "What-If" calculations, since it figures out what parts of a problem are missing and uses the rest to solve them. This means you don't have to rewrite the equations to put the unknowns on the left side, which is tedious and error-prone.

I wonder if you would be willing to post the equations and derivations, and I will put them in Mercury to see what it can do. I used to do this kind of analysis back in the 50's, but ended up never having to use it, so it all rusted away. I even downloaded the Radiotron Designers Handbook to study the Theory of Networks in Chapter 4, but haven't even found time to do that yet:

Working with your equations would go a long way to getting me started brushing up on the basics.

One other note is I don't know how to add Miller capacitance to the circuit, since the inverter should be saturated most of the time. But there will be stray capacitance between the traces and ic pins, and it is interesting to see the large effect it has due to the 180 degree phase reversal through the tank. I added another capacitor, C4, to show this. Increasing it to only 1 pf drops the resonant frequency significantly.

Thanks for a very interesting and informative post. There are many fascinating topics in electronics, but few are as captivating as the magic of resonance, especially in oscillators:)

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Here's the ASC file:

Version 4 SHEET 1 880 680 WIRE -16 16 -256 16 WIRE 320 16 48 16 WIRE 160 64 64 64 WIRE 320 64 320 16 WIRE 320 64 224 64 WIRE -256 144 -256 16 WIRE -192 144 -256 144 WIRE -112 144 -192 144 WIRE 16 144 -32 144 WIRE 64 144 64 64 WIRE 64 144 16 144 WIRE 96 144 64 144 WIRE 208 144 176 144 WIRE 320 144 320 64 WIRE 320 144 288 144 WIRE 368 144 320 144 WIRE -256 192 -256 144 WIRE 16 208 16 144 WIRE 320 208 320 144 WIRE -256 320 -256 272 WIRE 16 320 16 272 WIRE 320 320 320 272 FLAG -256 320 0 FLAG 16 320 0 FLAG 320 320 0 FLAG -192 144 Vin FLAG 368 144 Vout FLAG 16 144 VCap SYMBOL cap 0 208 R0 SYMATTR InstName C1 SYMATTR Value 1.2814nf SYMBOL cap 304 208 R0 SYMATTR InstName C2 SYMATTR Value 256.29pf SYMBOL ind 80 160 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 4.7µh SYMBOL res 192 128 M90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 4.92 SYMBOL res -128 128 M90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 750 SYMBOL voltage -256 176 R0 WINDOW 123 24 134 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC 1 SYMATTR InstName V1 SYMATTR Value SINE(0 1.5 5000000) SYMBOL cap 160 80 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C3 SYMATTR Value 2pf SYMBOL cap -16 32 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C4 SYMATTR Value 1pf TEXT -136 -48 Left 0 ;'5 MHz pi Network C1 = 5C2 TEXT -216 360 Left 0 !.ac lin 20k 4.88e6 5.12e6

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Here's the PLT file:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The end.

Ok Mike, it seems to go like this.......

Recall that Vout has to be 180 degrees lagging from Vin.

This then means that I(Cout) leads Vout by 90 degrees, and consequentially I(Cout) MUST lag Vin by 90 degrees.

But as noted earlier the R+L+Cout branch can never reach full a 90 deg of lag between the applied voltage (Vcap) and the resultant current in it.

So to get the full 90 degrees of lag the Vcap voltage has to LAG by the shortfall. With a resistive feed the pi-network has to run at a frequency where the Zin is slightly capacitive.

We saw about a 3.8 deg of shortfall and I can roughly account for about 2.8 deg of this.

At 5MHz the pi-network Zin looks like an 1100 ohm R, in series with a 431pF C, and is fed with a 3k3. A few quick sums shows that Vcap lags Vin by about 2.84 deg.

I *think* the 1 degree difference is because the overall circuit gets the 180 degrees at 5.002MHz, not 5.

Brute force and ignorance. Ignore the fact that it is a parallel tuned circuit and just regard the pi as a Cin in parallel with the R+L+Cout branch.

Do some algebra to get Zin (as previously), ignore the small capacitive element and just use the resistive part. Use the fact that w.L = (1/w.C1) + (1/w.C2) and K = Cin/Cout to get rid of references to Cin or Cout.

It's then a resistive divider from Vin to Vcap, and multiply that by K to get the overall Gain.

Differentiate to get dG/dK, and equate to zero.

A quick note on the above. I seem to be having a problem or misunderstanding the LTspice phase plots.

That 105 Deg/MHz result above was done by measuring off the plot of the phase shift for V(Vin,Vout), ie the difference between Vin and Vout.

Then last night I also casually looked at Vout alone. It's phase shift plot was much larger, showing about 600 D/MHz. Moreover the size of the D/MHz continually increased with K, which is what I had mentally expected for reducing values of Cout, rather than the peak that LTspice apparently showed.

I'm still puzzled by this because Vin is the zero-phase reference input, so the phase plots of V(Vin,Vout) and Vout should be the same.

I had assumed Mike that the very high Q of a crystal meant that there would be no problems in the Gain of the network. Far from it, the Gain might have to be throttled back to avoid overdriving the gate or the crystal. Is this not so?

Note by the way that all sums have assumed a perfect amplifier with no phase lag. This would have to be factored in at some time.

They are fairly long winded and not easy in ascii, so it would have to be a post in abse or via email.

OK, thanks. I will study this in LTspice and see how it all fits together. The 1 degree could easily be roundoff error. I'll redo the LTspice file and enter the component values to more decimal places.

But I'm still hazy on how the I(R1) phase angle can go negative.

OK, I will have to go through this carefully also:)

OK, another part to study in detail:)

Yes, most of the circuits I have looked at so far overdrive the crystal by a factor of ten or more, especially at higher frequencies. Most people do not measure this since it is so hard to do. But the technique to initialize the tank energy at the start of the SPICE analysis makes it very easy.

However, we have not reached that point yet. In my mind, we are still trying to get the equations for a simple pi network, and a method to solve them easily. Afterwards, we still have to add the motional capacitance of the crystal and boost the Q.

Yes, this also raises some questions. Is the phase lag near zero when the device is operated in the linear region, then it increases to the values shown on the datasheet when it runs at high level? If so, how do we account for that?

Didn't you do some work on CMOS inverters a while back - maybe five years or so? I seem to recall you posting some info on gain and maybe other things.

I would be very happy if you could email them to me. You can use the email address on my contact page:

Then if it's OK with you, I will put them on a web page so we can refer to them.

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Those numbers kept for the little sketch below.

At 5MHz I(R1) should lead V1 by about 1 deg, ie, damn near resistive. Perhaps a vector diagram would help? ASCII art follows.

R1,3k3 V1---/\\/\\----+ five years or so? I seem to recall you posting some info on

Vague memory. I'll see if I can find any data.

Doesn't work... no bounce, no reply. :(

I'll try again.