RS-232

Wrong. You could have easily looked it up. Look here:

regards, Wolfgang

generally the start bit is a high and the stop bit(s) is low so you can definately see the start bit.

in idle, the output will be low (usually left there after the last character transmitted, you see the line go high and wait for 150% of the bit width - this waits for the start bit to end and you should be half way into the first bit of "real" data. you then sample and wait

each time you sample a bit, you right shift (RS232 is LSB first) it into a register so that after 8 cycles, you have one byte of info. Stash that somewhere and repeat the above for each character.

If the stop bit(s) were not low, you wouldn't be able to see the start bit go high. If you are transmitting 0xFF, the only low bit in the whole 10 bits (if using 8N1 - 8 data bits, no parity, 1 stop bit - very common format) is the stop bit so you need to have a low in order to see the next high-going start bit.

On 08/10/2006 the venerable feebo etched in runes:

The OP asked about logic levels and not voltages. In RS232 anything in the range +3V to +24V represents logic 0 and -3V to -24V represents logic 1. The area between +3V and -3V is undefined. So the start bit is logic 0 and the stop bits/line idle are logic 1.

Well, to be somewhat pedantic, RS232 doesn't really specify the data format; it specifies the signalling levels :)

That said, JohnB is completely correct.

For the OP - easy enough to look up. All control signals are active when logically '0' on RS232. Start -> logical 0, Stop -> logical 1.

Cheers

PeteS

assuming you mean asynchronous RS232: (like PCs do)

start is a space (logical 0, +3 to +15V) stop is a mark (logical 1 -3 to -15V)

idle is a mark.

Bye. Jasen