3 line to 7 line decoder, got a name?

I was trying to design in a Gray code scheme but I can't see how it applies to binary weighted resistors, so fell back to this scheme where higher power resistors are switched on in a sequence to limit the switching spike energy so it can be easily filtered.

Besides, I didn't like the idea of half and quarter power resistor banks anyway, as the switches would need heatsinking (fullscale ~30A). So I trade lots more MOSFET switches for no heatsinking.

The low power end of the DAC will go through a power opamp that will also compensate the large resistor 5% tolerance variation. I'll be using ~30k count ADC resolution for feedback.

Grant.

Is making one of any use to you?

Something very like that, yes. If I decide on making a rough power circuit tester with an error comparator and up-down counter --> it's what I was thinking of, but I was hoping to skip all those diodes :)

Sure, it's the obvious (one off) solution, but one certainly couldn't call it 'elegant' ;^) But then the resistor banks I'm making for this wont be elegant either. A little tower stacked up over a 120mm fan, fabricated from blank PCB. Something to do, 'cos I don't always get the same enjoyment writing code.

I'll put up some photos one day, for the curious...

Grant.

But he only has three input bits. ;-)

Sure they have. It's generally easier and cheaper to do it one of the many ways suggested than to have an ASSP for the function.

--- If all you want is a switchable load box then, arguably, the easiest way to do it would be to use resistors weighted in a binary sequence driven by a counter's Qs. View in Courier:

. DUT . +------+ . | + - | . +-------------------+ +-+--+-+ .CLK>---|> | | | . _ | _ | +----+ | .U/D>---|U/D | | | | . | Q3 Q2 Q1 Q0 | [8R] | | . +-----+---+---+---+-+ | | | . | | | | D | | . | | | +------G | | . | | | S | | . | | | | | | . | | | +----|--+ . | | | | | . | | | +----+ | . | | | | | | . | | | [4R] | | . | | | | | | . | | | D | | . | | +----------G | | . | | S | | . | | | | | . | | +----|--+ . | | | | . | | +----+ | . | | | | | . | | [2R] | | . | | | | | . | | D | | . | +--------------G | | . | S | | . | | | | . | +----|--+ . | | | . | +----+ | . | | | . | [R] | . | | | . | D | . +------------------G | . S | . | | . +-------+

JF

Oh sure, that's where this started, but...

The decoder is used for MSB weighted resistors in the bank to reduce maximum switching glitch from 1/2 to 1/8 fullscale, also lets me use MOSFETs without heatsinks, though that's a weaker argument 'cos I could have paralleled some for the MSBs anyway.

The remaining mid LSBs have binary weighted resistors down to about

The output terminals present near DC quiet to around mV levels, have a very gentle dV/dt.

Previous prototypes used a linear approach (like half a big audio power amp -- eight pass transistors on a live 0.3'C/W heatsink) but they drifted over temperature and would not perform down to the small mV levels like I wanted.

So this is a hybrid approach with isolated drive to the big power stuff, and a PIC to get the fine control end where I want it.

Besides, specs changed over the time I been looking at this, now the 'client' wants set'n'forget operation which requires a sample hold to remember nearest mV (1:40k resolution) for several hours, and generation of mV/minute ramp rates -- stuff I'd be mad to try implementing totally analog ;)

Grant.