Usually CMOS outputs swing very close to the power rails, with no load. The only static load on your output is leakage currents. Are you sure about the 3.1V measurement? Did you use a bench multimeter or a scope? I'd be surprised if the difference is more than a couple of tens of mV with no load.
If it's a Z8 Encore! that you're working with , the 2.4V spec is with a (relatively) massive 2mA load on the output.
It's commonly done and is reliable. The output swing is typically essentially hard to the rails unless you've got something odd with your processor, so 3.3 is a pretty good drive for a TTL high (2.4V minimum). If the 3.3V device has CMOS-level or ST inputs, that's another matter.
The Vih and Vil of "TTL" level CMOS inputs change with supply voltage, but not proportionally. When you have two entirely different supply regulators, of course, you have to consider worst-case for both.
SCL and SDA will be driven by an open-drain output with pullup to Vdd, so the Voh on the datasheet doesn't really apply.
Again, there are only leakage currents. Maximum input current (70°C) is 12uA on SCL/SDA, so with a 10K pullup that will mean 120mV of drop across the pullup resistor. You have to add any other leakages in your circuit (probably just the output leakage on the micro) if you want to check how much margin there is.
Best regards, Spehro Pefhany