This also addresses a message I posted a couple of days ago. I am trying to design an analog switch for a DRAM application.
The problem is "a drastic difference" in behavior when I used cadence tool to pspice. My schematic is a very simple test circuit where the gate of an NMOS is made logic low (-3 V). I am putting a value 100mV on one end of the NMOS switch (say, drain). A capacitor is connected to the other side of the switch with a value 1pF. Now, the problem is that, when I run transient analysis, I am seeing a voltage of about 90+ mV on the capacitor net. How is this possible? The transistor is turned off and I should ideally not see anything except leakage.
This was the issue when I used spectre simuation in cadence. I did the same experiment using Orcad pspice and it works as I expect it to. Before I was working with pspice, I thought it might be a leakage problem associated with the internal diode inside the MOSFET and to check that out, I put a transistor whose gate was connected to inverse clock, before the capacitor. In this setup, if the main transistor is on, then the other transistor is off. I did this to provide a low impedence path to the leakage, if any. So, when the main transistor or the switch is off, any leakage may flow through this low impedence path created by the second transistor and if the switch is on, the second transistor functions as open circuit and should not affect my circut. This setup works.
I am really surprised because, this logically baffles me. Further, how come Pspice gives me a different behavior (which I believe to be correct) in the first case?
Any help is greatly appreciated. I hope I have posed the question clearly.
Regards, Saran