Has anyone come across a schematic for a PC parallel port SCSI controller? I think I've got one figured out on paper but I'm surprised nobody's produced a hobby version already and it seems a shame to reinvent the wheel.
For my particular application I'm only talking to old SCSI-1 devices so lack of speed is not a problem - hence I'm hoping I'll be able to get away with a dumb interface just using a few buffers and latches, rather than a microprocessor controlled solution with buffering which handles the SCSI protocol. I don't yet know if I'm going to hit timeout problems though...
Some of the older parallel port scanners have cables that apparently do the parallel port/scsi interface work. You might find some info in those types of areas.
That would be quite useful. I'm curious to see how other designs have managed to get around the lack of output lines on a PC's parallel port.
I figure I need octal tri-state latches for data out / in (I'm assuming a bi-directional port) and for the outgoing SCSI control lines.
There are enough input lines for me put all of the 'incoming' SCSI control lines via a buffer straight into the port.
Still means I need three seperate latches though, which means two of the parallel port outputs are needed to control a 2-to-4 line decoder to select which latch to address.
Problem is that any one latch needs to be held in a latched state whilst I select a different latch using the decoder - so there are two possible sequences for the latches:
1) select latch using decoder
2) latch a low into the selected latch's control pin (assuming control is active low for the moment) in order to latch data.
3) latch a low into the selected latch's output enable pin (again assuming active low).
or:
1) select latch using decoder
2) latch a high into the selected latch's output enable pin to set the outputs to high impedance.
3) latch a high into the selected latch's control pin in order to stop latching data and make internal register follow inputs.
in other words ideally I need three controlling lines here and only have two spare available (as the PC parallel port only has four output control lines and I need two for the decoder). When "setting" the latch I need to latch data first, then set outputs to low impedance, but when "clearing" the latch I need to do the opposite and set the outputs to high impedance
*before* clearing the latch.
I'm curious as to how this has been done in the past given the small number of output lines available on the PC's port. Unless of course all the designs work in slower nibble mode rather than dealing with 8 bits at a time...
Makers such as Adtron have adapters that go from IDE to SCSI, or USB to SCSI. It's not worth it to mess with parallel ports when you can get a plug and play solution for a few tens of dollars.
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