Hi!
I have a [MCU] core running at 50MHz which I use for generating patterns/reading status of some other logic, mapped on the same fpga (spartan3).
I have noticed the timing after placement/routing is varying with incremental changes; just changing an initial value could make the timing to fail (I saw numbers like 47 and 45 MHz). The logic seems to run on my board but that does not mean it will not fail on some other board/fpga chip.
My guess is everything is caused by a difference in the placement; from time to time the placer starts from the wrong place [seed?] and the resulting design will fail timing. Loading the design in fpga_editor I can see different arrangements for the BRAM blocks the design is using (5 out of 12 available).
Did you have similar experiences? What can one do to expect more consistent results?
I am using Webpack 9.1(0.2). I don't think Webpack version is relevant, I seem to remember same thing with 7.1 version.
-- mmihai