Hello all. I have a very strange thing happening with my FPGA.
I have Xilinx Spartan-3E FPGA, that I am programming to count external pulses in 1us time bins. The way I'm doing that, is I have a pulse index counter, that increments whenever there's a rising edge on the pulse counter. (No resetting, no enabling, etc.) Then I have another loop that checks the count on the pulse counter every 1us, and writes the "pulse index" to an off-board SDRAM chip.
So I have an always block like this:
always @(posedge pulse_in) begin pulse_index