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Ring Oscillator Redux

There was a thread about ring oscillators recently. I tried to build one in a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the ring of inverters into a single inverter. I'm sure there is a simple way to preserve the logic from being pruned by the tools by means of a constraint, but I can't figure it out. What's the secret, short of routing each inverter's output to an IOB to prevent pruning?

The frequency of the oscillator is not critical so I'm not worried about placement or routing.

-Kevin

Reply to
Kevin Neilson
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Maybe the KEEP attribute would work?

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--
Ben Jackson

http://www.ben.com/
Reply to
Ben Jackson

Ben,

KEEP or SAVE.

Aust> >

Reply to
Austin Lesea

Thanks, guys. I used KEEP and SAVE and had to really fight the tools to keep everything from getting pruned and merged, but I finally got it to work.

-Kevin

Reply to
Kevin Neilson

Until you compile it on a different revision of the tools :-O

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

I also found it helpful to constrain the routing to obtain consistent timing. As Peter mentioned last time, you could also try using the carry chain for delay, and that considerably reduces the variation due to routing differences.

/Siva

primitives for

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Reply to
Siva Velusamy

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