I'm trying to frequency match a number of ring oscillators placed over a Xilinx FPGA. The intention is to use the oscillators as thermometers.
Each ring oscillator is a chain of 7 LUTs configured as NOT gates. The problem is that the frequency output varies by as much as 10% (e.g 150 -
165Mhz). While it is not absolutely essential to match the frequencies, I would like to know the source of this difference. Could any of you throw some light on this? Thanks.The LUTs have been placed using RLOCs, so the oscillators have the same logic structure. Is it possible that the routing method is different? If so, is it possible to constrain them to be the same?
Thanks, Siva
--------------------------- "In the end, everything is a gag." - Charlie Chaplin