Here are parts of the synthesis reports for the naked core of an KCPSM3 in a SpartanII (XC2S100):
PacoBlaze: =========================================================================
- ========================================================================= Final Results RTL Top Level Output File Name : kcpsmx.ngr Top Level Output File Name : kcpsmx Output Format : NGC Optimization Goal : Area Keep Hierarchy : NO
Design Statistics # IOs : 58
Macro Statistics : # RAM : 3 # 16x8-bit dual-port distributed RAM: 1 # 32x10-bit single-port distributed RAM: 1 # 64x8-bit single-port distributed RAM: 1 # Registers : 19 # 1-bit register : 16 # 10-bit register : 1 # 5-bit register : 2 # Multiplexers : 10 # 1-bit 4-to-1 multiplexer : 1 # 2-to-1 multiplexer : 9 # Adders/Subtractors : 3 # 10-bit adder : 1 # 5-bit addsub : 1 # 8-bit adder carry in/out : 1 # Xors : 1 # 1-bit xor8 : 1
Cell Usage : # BELS : 273 # GND : 1 # LUT1 : 13 # LUT2 : 16 # LUT3 : 108 # LUT4 : 91 # MUXCY : 21 # MUXF5 : 1 # VCC : 1 # XORCY : 21 # FlipFlops/Latches : 46 # FDE : 2 # FDR : 11 # FDRE : 29 # FDRS : 2 # FDS : 2 # RAMS : 34 # RAM16X1D : 8 # RAM32X1S : 26 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 57 # IBUF : 28 # OBUF : 29 =========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s100etq144-6
Number of Slices: 200 out of 1200 16% Number of Slice Flip Flops: 46 out of 2400 1% Number of 4 input LUTs: 288 out of 2400 12% Number of bonded IOBs: 57 out of 102 55% Number of GCLKs: 1 out of 4 25%
========================================================================= TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ clk | BUFGP | 80 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------- Speed Grade: -6
Minimum period: 21.627ns (Maximum Frequency: 46.238MHz) Minimum input arrival time before clock: 24.700ns Maximum output required time after clock: 8.320ns Maximum combinational path delay: 10.734ns
Timing Detail:
-------------- All values displayed in nanoseconds (ns)
------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 21.627ns (Levels of Logic = 16) Source: register_Mram_dpr_inst_ramx_3 (RAM) Destination: zero (FF) Source Clock: clk rising Destination Clock: clk rising
Data Path: register_Mram_dpr_inst_ramx_3 to zero Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ RAM16X1D:WCLK->DPO 2 1.568 1.150 register_Mram_dpr_inst_ramx_3 (register_y_data_out) LUT3:I2->O 35 0.468 3.375 scratch_address1 (scratch_address) LUT3:I2->O 1 0.468 0.000 alu_Madd__n0021_inst_lut2_171 (alu_Madd__n0021_inst_lut2_17) MUXCY:S->O 1 0.515 0.000 alu_Madd__n0021_inst_cy_18 (alu_Madd__n0021_inst_cy_18) MUXCY:CI->O 1 0.058 0.000 alu_Madd__n0021_inst_cy_19 (alu_Madd__n0021_inst_cy_19) MUXCY:CI->O 1 0.058 0.000 alu_Madd__n0021_inst_cy_20 (alu_Madd__n0021_inst_cy_20) MUXCY:CI->O 1 0.058 0.000 alu_Madd__n0021_inst_cy_21 (alu_Madd__n0021_inst_cy_21) XORCY:CI->O 1 0.648 0.920 alu_Madd__n0021_inst_sum_22 (alu_addsub_result) LUT4:I1->O 1 0.468 0.920 alu__old_result_653 (CHOICE603) LUT4:I3->O 3 0.468 1.320 alu__old_result_661 (alu_result) LUT3:I1->O 1 0.468 0.000 alu_Mmux__n0004_inst_mux_f5_0111_G (N11696) MUXF5:I1->O 2 0.403 1.150 alu_Mmux__n0004_inst_mux_f5_0111 (alu_shift_bit) LUT4:I1->O 1 0.468 0.920 alu__old_result_629 (CHOICE463) LUT4:I2->O 3 0.468 1.320 alu__old_result_661 (alu_result) LUT3:I1->O 1 0.468 0.920 Mmux__n0016_Result24 (CHOICE447) LUT3:I1->O 1 0.468 0.920 Mmux__n0016_Result49_SW0 (N11635) LUT4:I3->O 1 0.468 0.000 Mmux__n0016_Result49 (N10428) FDRE:D 0.724 zero
---------------------------------------- Total 21.627ns (8.712ns logic, 12.915ns route) (40.3% logic, 59.7% route)
------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 24.700ns (Levels of Logic = 14) Source: instruction (PAD) Destination: zero (FF) Destination Clock: clk rising
Data Path: instruction to zero Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ IBUF:I->O 30 0.797 3.250 instruction_17_IBUF (instruction_17_IBUF) LUT3:I1->O 3 0.468 1.320 alu_Ker71491 (alu_N7151) LUT3:I0->O 9 0.468 2.150 alu__n00191 (alu__n0019) LUT3:I0->O 8 0.468 2.050 alu_Ker707067 (N9028) LUT3:I2->O 1 0.468 0.920 alu__old_result_653_SW0 (N11655) LUT4:I2->O 1 0.468 0.920 alu__old_result_653 (CHOICE603) LUT4:I3->O 3 0.468 1.320 alu__old_result_661 (alu_result) LUT3:I1->O 1 0.468 0.000 alu_Mmux__n0004_inst_mux_f5_0111_G (N11696) MUXF5:I1->O 2 0.403 1.150 alu_Mmux__n0004_inst_mux_f5_0111 (alu_shift_bit) LUT4:I1->O 1 0.468 0.920 alu__old_result_629 (CHOICE463) LUT4:I2->O 3 0.468 1.320 alu__old_result_661 (alu_result) LUT3:I1->O 1 0.468 0.920 Mmux__n0016_Result24 (CHOICE447) LUT3:I1->O 1 0.468 0.920 Mmux__n0016_Result49_SW0 (N11635) LUT4:I3->O 1 0.468 0.000 Mmux__n0016_Result49 (N10428) FDRE:D 0.724 zero
---------------------------------------- Total 24.700ns (7.540ns logic, 17.160ns route) (30.5% logic, 69.5% route)
------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 8.320ns (Levels of Logic = 1) Source: register_Mram_dpr_inst_ramx_7 (RAM) Destination: out_port (PAD) Source Clock: clk rising
Data Path: register_Mram_dpr_inst_ramx_7 to out_port Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ RAM16X1D:WCLK->SPO 9 1.568 2.150 register_Mram_dpr_inst_ramx_7 (out_port_7_OBUF) OBUF:I->O 4.602 out_port_7_OBUF (out_port)
---------------------------------------- Total 8.320ns (6.170ns logic, 2.150ns route) (74.2% logic, 25.8% route)
------------------------------------------------------------------------- Timing constraint: Default path analysis Delay: 10.734ns (Levels of Logic = 3) Source: instruction (PAD) Destination: out_port (PAD)
Data Path: instruction to out_port Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ IBUF:I->O 10 0.797 2.250 instruction_10_IBUF (instruction_10_IBUF) RAM16X1D:A2->SPO 9 0.935 2.150 register_Mram_dpr_inst_ramx_1 (out_port_1_OBUF) OBUF:I->O 4.602 out_port_1_OBUF (out_port)
---------------------------------------- Total 10.734ns (6.334ns logic, 4.400ns route) (59.0% logic, 41.0% route)
PicoBlaze: =========================================================================
- ========================================================================= Final Results RTL Top Level Output File Name : kcpsm3.ngr Top Level Output File Name : kcpsm3 Output Format : NGC Optimization Goal : Area Keep Hierarchy : NO
Design Statistics # IOs : 58
Cell Usage : # BELS : 196 # GND : 1 # INV : 3 # LUT1 : 2 # LUT2 : 6 # LUT3 : 71 # LUT4 : 30 # MUXCY : 39 # MUXF5 : 9 # VCC : 1 # XORCY : 34 # FlipFlops/Latches : 86 # FD : 21 # FDE : 2 # FDR : 33 # FDRE : 8 # FDRSE : 20 # FDS : 2 # RAMS : 18 # RAM16X1D : 8 # RAM32X1S : 10 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 57 # IBUF : 28 # OBUF : 29 # Others : 8 # RAM64X1S : 8 =========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s100etq144-6
Number of Slices: 129 out of 1200 10% Number of Slice Flip Flops: 86 out of 2400 3% Number of 4 input LUTs: 169 out of 2400 7% Number of bonded IOBs: 57 out of 102 55% Number of GCLKs: 1 out of 4 25%
========================================================================= TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ clk | BUFGP | 104 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------- Speed Grade: -6
Minimum period: 9.767ns (Maximum Frequency: 102.386MHz) Minimum input arrival time before clock: 10.997ns Maximum output required time after clock: 8.878ns Maximum combinational path delay: 11.292ns
Timing Detail:
-------------- All values displayed in nanoseconds (ns)
------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 9.767ns (Levels of Logic = 13) Source: carry_flag_flop (FF) Destination: register_bit9 (FF) Source Clock: clk rising Destination Clock: clk rising
Data Path: carry_flag_flop to register_bit9 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ FDRE:C->Q 4 0.992 1.520 carry_flag_flop (carry_flag_flop) LUT4:I0->O 2 0.468 1.150 condition_met_lut (condition_met) LUT3:I1->O 11 0.468 2.350 normal_count_lut (normal_count) LUT3:I0->O 1 0.468 0.000 value_select_mux0 (pc_value) MUXCY:S->O 1 0.515 0.000 pc_value_muxcy0 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy1 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy2 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy3 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy4 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy5 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy6 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy7 (pc_value_carry) MUXCY:CI->O 0 0.058 0.000 pc_value_muxcy8 (pc_value_carry) XORCY:CI->O 2 0.648 0.000 pc_value_xor9 (inc_pc_value) FDRSE:D 0.724 register_bit9
---------------------------------------- Total 9.767ns (4.747ns logic, 5.020ns route) (48.6% logic, 51.4% route)
------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 10.997ns (Levels of Logic = 14) Source: instruction (PAD) Destination: register_bit9 (FF) Destination Clock: clk rising
Data Path: instruction to register_bit9 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ IBUF:I->O 27 0.797 3.175 instruction_14_IBUF (instruction_14_IBUF) LUT4:I0->O 1 0.468 0.920 move_group_lut (move_group) LUT3:I2->O 11 0.468 2.350 normal_count_lut (normal_count) LUT3:I0->O 1 0.468 0.000 value_select_mux0 (pc_value) MUXCY:S->O 1 0.515 0.000 pc_value_muxcy0 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy1 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy2 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy3 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy4 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy5 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy6 (pc_value_carry) MUXCY:CI->O 1 0.058 0.000 pc_value_muxcy7 (pc_value_carry) MUXCY:CI->O 0 0.058 0.000 pc_value_muxcy8 (pc_value_carry) XORCY:CI->O 2 0.648 0.000 pc_value_xor9 (inc_pc_value) FDRSE:D 0.724 register_bit9
---------------------------------------- Total 10.997ns (4.552ns logic, 6.445ns route) (41.4% logic, 58.6% route)
------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 8.878ns (Levels of Logic = 2) Source: register_bit70 (RAM) Destination: port_id (PAD) Source Clock: clk rising
Data Path: register_bit70 to port_id Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ RAM16X1D:WCLK->DPO 1 1.568 0.920 register_bit70 (sy) LUT3:I2->O 3 0.468 1.320 operand_select_mux7 (port_id_7_OBUF) OBUF:I->O 4.602 port_id_7_OBUF (port_id)
---------------------------------------- Total 8.878ns (6.638ns logic, 2.240ns route) (74.8% logic, 25.2% route)
------------------------------------------------------------------------- Timing constraint: Default path analysis Delay: 11.292ns (Levels of Logic = 4) Source: instruction (PAD) Destination: port_id (PAD)
Data Path: instruction to port_id Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ IBUF:I->O 10 0.797 2.250 instruction_4_IBUF (instruction_4_IBUF) RAM16X1D:DPRA0->DPO 1 0.935 0.920 register_bit00 (sy) LUT3:I2->O 3 0.468 1.320 operand_select_mux0 (port_id_0_OBUF) OBUF:I->O 4.602 port_id_0_OBUF (port_id)
---------------------------------------- Total 11.292ns (6.802ns logic, 4.490ns route) (60.2% logic, 39.8% route)