Overshoot/undershoot towards 2V4000

Howdy Gunter,

I'm probably missing something here due to lack of sleep, but my first reaction was that a 100 mA current spike into a tri-stated FPGA pin doesn't seem quite right. I'm sure someone else will speak up on that part of the issue.

Regardless, you could probably reduce the overshoot by using a ALVCHR instead - they contain a ~25 Ohm series resistor. Another idea would be to use a lower VCC (either in the ALVC, or on a related family that may have higher input voltage tolerance like LVC or AVC).

Good luck,

Marc

Gunter,

The protection diodes are clamping the overshoot and undershoot. They will not be damaged, but your signal integrity is terrible, you will have excessive jitter, and that may lead to bit errors, and other behavior that you will not like at all.

I doubt the simulation is pessimistic, as I get the same results, and often worse when too strong a driver is used unterminated.

I suggest a small series resistor at the driver to better match the lines. Perhaps somewhere from 22 ohms to 43 ohms. Simulate until you have the best choice for the slow/weak and fast/strong IBIS model corners.

Oh, and thank you for using IBIS before you built the board. We are happy (and you are happy) when you fix problems before the board layout.

Aust> Hi,

Austin,

thanks very much for your answer. It's in a sense good to know that the simulation seems to be accurate - despite the fact that we then have to worry more about signals and spend more real estate for terminations. What makes me wonder, though, is that the simulations also said that one cannot even connect two FPGAs directly without violating undershoot limits - this doesn't reflect reality. What I really would like to know is whether or not I can damage the 2V4000 chip with strong over/undershoot. You said that the clamp diodes will withstand that stress, but what about the MOS transistors? The voltage across the gate oxide might become too large if excessive current causes a large voltage drop across the clamp diodes. I couldn't find anything on this topic in the VII-docs. Can you shed some light on this?

Thanks very much Gunter

Marc,

thanks very much for your answer. Using transceivers with built-in series resistors would be a solution. Unfortunately, I'm planning on using the 32501 36-bit transceiver, of which no version with resistors is available. To my knowledge, this chip exists in only one additional technology, LVCH, which is just as fast.

Cheers Gunter

Gunther,

To connect two fpgas together, one should use the proper standard.

LVDCI works, as does LVCMOS 6 mA (no external resistors required) with no simulations (as they are both 50 ohms and will match almost any pcb trace well enough).

Any other standards require some SI engineering.

The Virtex II family uses 0.35u IO, and they are intrinsically protected by the ESD structures. You can not break them with overshoot and undershoot. But you can create functional problems, and even change BRAM and config bit contents if you slap the substrate silly with currents!

The Virtex II Pro, S3, and V4 families uses faster 0.25u transistors, and the reliabily is affected if the IO pin is forced to a voltage below ground (> 4.05V stress on the pmos output transistor = Vcco - undershoot < 4.05V). This is detailed in the data sheet under the abs max stresses.

Not paying attention to signal integrity is just playing 'Russian Roulette' with more than one chamber loaded -- very risky business.

Austin

Gunter Knittel wrote:

Austin,

thanks. Absolutely most useful information. Thanks also for making such a clear statement. However, concerning SI, I can assure you that you are preaching to the converted. I was just asking because I have a number of low-rate control signals which have more than enough time to settle. Of course this doesn't reduce ringing, so I'm going to use series resistors at any output driving towards the FPGA.

Thanks again Gunter