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OSD implementation in FPGA

Hi,

we have a "Video Monitor On-Screen Display" device from Motorola Semiconductors. (MC141581P2) The problem is that this device has been discontinued. Instead of looking for a new device we are thinking about implementing our own OSD device in a FPGA.

Where do you think could arise problems when using a FPGA ?

I think the main drawback is that FPGAs are not able to generate stable clocks out off a internal PLL when the input clock of the PLL changes dynamically. Is that correct ? Or do such PLLs exist in FPGAs ?

Thank you for your opinion.

Rgds Andr=E9

Reply to
ALuPin
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We use FPGA to generate OSD. The only special requirement is to use an external good quality VCO.

Reply to
Zara

Hi Zara,

what kind of OSD have you implemented ?

Are there general papers you can recommend ?

Rgds Andr=E9

Reply to
ALuPin

Our OSD works on SDI digital video.

You may find in xilinx website a lot of applications on SDI processing. Maintining enough mental distance, almost all of them are applicable to lots of video designs (not only OSD).

regards

Zara

Reply to
Zara

I can imagine wanting to sync to an ordinary video camera as used in security applications. I guess that would be slightly harder.

A long time ago I saw an article where a 6845 was used as part of a PLL to sync video frame addresses with a video signal. The circuit compared the SYNC signals from both sources to decide whether to ramp the clock up or down.

I have the circuit somewhere on my PC, if anybody wants it.

Reply to
Kryten

A while back I did a video design that brought the image in on the incoming video timing, transferred it to a slightly fast local clock for the processing and then returned it to the incoming video timing at the output. We did it this way to avoid using external PLLs. Just offering it as an alternative approach.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

My last design does OSD (and other things, of course) using this same approach.

The fpga + sdram runs at the pixel clock doubled by DLL (Spartan2E), 54 Mhz.

The stream is digitized, OSD with graphics is super-imposed on the stream, the played back. The sdram stores stills when needed.

The DLL can lock to the sligthly jittering pixel clock (that's locked to line syncs). Made more than 2k pcs with no problems.

Reply to
Antonio Pasini

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