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MPMC2 : npi issues

Hi,

I am exploring the possibility to use the npi(native port interface) towards the MPMC2(multi port memory controller). I will use the BRAM as FIFO on the write side of the RAM

Does anyone have any experience with this ? After reading the documentation

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I am left with a lot of questions. I am not able to find any other documentation/user experience.

I want to use the timing as described in figure 37: Word write

My main questions are:

  1. How long can the delay between AddrReq and AddrAck be ? If this can be of arbitrary length(as claimed in the documentation) one need to buffer the data before the npi to ensure not to loose data.

  1. Our memory has 32 bits datalength, while npi uses 64 bits. How is the data alignment between this two busses ?

Any comments/answers will be greatly appreciated !

Reply to
ivo
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  1. Your request wll be served based on the selected priority of the NPI port in mpmc2 core. Data itself are buffered in WR and RD fifos inside the mpmc2, and are independend of address cycle. Then you don't need to wait untill AddrAck will be asserted to write the data to mpmc2.

  1. Regardless of the memory width look at the NPI that it can store up to 8 bytes in one shot. You can also select which bytes you want to store by PI_BE signals.

Reply to
leevv

towards the MPMC2(multi port memory controller).

I am about to start testing a NPI periperal, so soon I will have some experience :)

/Mikhail

Reply to
MM

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