microprocessor on fpga problems

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Hi,

Just wondering what could go wrong when synthesizing memories (i-
cache, d-cache, and write buffer) of microprocessors on fpga Xilinx
Virtex 5? Thanks!

Wei


Re: microprocessor on fpga problems
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anything ;)


Re: microprocessor on fpga problems


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You beat me to it!  Absolutely, where do you PLAN to put your mistakes?!

Jon


Re: microprocessor on fpga problems
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ROTFL
eh, really there are TOO MANY things that can go wrong.
also the OP question was really too generic :)

the frequency of the mistake is reverse proportional to the time left
to the deadline
hm, not very elegantly said, but think some will agree to that.
extreme TTM pressure will in most cases cause more mistakes to be
done.

there is nothing wrong making mistakes, what counts is ability to find
and fix them
quick no matter the deadline pressure and hopefully not to repeat them
too often ;)

so what can go wrong? if you are doing some own soft-core for
Virtex-5 ?
well how old is EDK? version is 9.2 now. I started to work and _fight_
with
the grandpa of EDK - a product called V2PDK. EDK has evolved great
deal.
but EDK 9.1SP2 can still not initialize a block of RAM when the size
of it is
say 24KB. If those 24KB are all you have and you need all of that, but
EDK 9.1SP2
is only able to initialize the first 16K and not the rest to due the
BMM mapping bug??
this means that the thing with SoC memory support aint so easy, or
that
hmm that Xilinx is doing a VERY BAD job at it, whatever you prefer.

if you start from scratch, you will certainly get something wrong.
this is what was the reasoning behind "anything"

Antti


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Thanks for all the inputs, well, I now get a better understanding of
the range of ram integration issues.
I (newbie) personally find it is not easy to debug this type of bugs
if something goes wrong with ram integration (either inferring or
instantiation), not knowing whether it is a synthesis tool problem or
verilog code problem. Nowadays, indeed anything can go wrong, core IPs
can go wrong, synthesis tools can go wrong (I once very wrongly trust
synplify_pro 8.8.0.2).


Re: microprocessor on fpga problems
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The biggest thing to go wrong would be synthesizing memories on a
Virtex5.

You want your code to -infer- memories, not synthesize them.

G.


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Generally I agree with that, but for some advanced features (different
input/output data widths, etc.) instantiation is the only way to do it
with built in logic.

As my English teacher taught me, "your code implies memories, the
synthesis tool infers memories", but nobody bothers with that
distinction anymore...

Andy


Re: microprocessor on fpga problems
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OK, let's try it this way:

You want your code to cause the synthesizer to infer memory, not
synthesize it.  Failing that, instantiate it directly.

Better?

G.


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