MICROBLAZE: user core problem

Hi,

I'm trying to connect a user peripheral to the Microblaze OPB bus. I have done all as mentioned in the "User Core Template for OPB (Slave Services Package 0) but without success.

I have added some code lines in the correponding places to match the IPIF to my user_core.

I have routed the Bus2IP_CS, Bus2IP_WrCE and Bus2IP_RdCE to some user leds in my development board and I haven't noticed any effect, so I imagine that I'm not accesing to my peripheral.

I have also checked the BASEADDR and the HIGHADDR and I think they're correct.

Here you are part of my MPD file

PARAMETER c_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE = 0xFF PARAMETER c_highaddr = 0x00000000, DT = std_logic_vector PARAMETER c_mir_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE = 0xFF PARAMETER c_mir_highaddr = 0x00000000, DT = std_logic_vector PARAMETER c_user_id_code = 3, DT = integer PARAMETER c_include_mir = 0, DT = integer PARAMETER c_opb_awidth = 32, DT = integer PARAMETER c_opb_dwidth = 32, DT = integer PARAMETER c_family = virtex2, DT = string

Note that I actualize "c_baseaddr" and "c_highaddr" parameters on the component as well as the "c_mir_baseaddr" and "c_mir_highaddr".

I'd be very grateful if someone could help me.

Thanks.

Arkaitz.

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arkaitz
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If you are attaching LEDs on these signals you will not see anything (maybe with an osilloscope) these signals are active only for an OPB bus transaction which will match your C_BASEADDRESS, depending on your OPB_Ack latency (transaction acknoledge) this will keep from 2 to 16 OPB_Clk periods so you need a very good eye to see a ~1 us blink. (assuming 100Mhz OPB_Clk)

Aurash

-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/

phone: 353 01 4032639 fax: 353 01 4640324

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Aurelian Lazarut

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