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Max7000s: how to use the enable of the dffe flip-flop?

Dear all,

I would like to register an address bus with the rising edge of the clk and if the LOAD is '1'. Below is my VHDL code.

The problem is that when I analyse and elaborate with QII and see the RTL view I see a mux that choose A_I or A_O with LOAD and the the output of this mux goes to a dffe flip-flops (the output of this flip-flops are feedback to the input of the mux). I would like to use the enable input of the dffe flip-flops instead of the mux with the LOAD. How to do this? is the RTL view related with what finally will be placed and routed?.

Thanks a lot and best regards,

Javi

entity DIR_LATCH is port( A_O: out std_logic_vector ( 18 downto 2 ); LOAD: in std_logic; CLK_I: in std_logic; A_I: in std_logic_vector ( 18 downto 2) ); end entity DIR_LATCH;

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-- Definicion de la Arquitectura

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architecture DIR_LATCH_A1 of DIR_LATCH is

begin

----------------------------------------------------------------------------- -- Definicion de la Arquitectura -----------------------------------------------------------------------------

ADR_REG: process ( CLK_I ) begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2)

Reply to
javid
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Oh my that's alot of typing (and very prone to typos). I believe the problem is that you have more than one controlling if statement within the process (in this case, more than one rising edge statement). But the reality of the matter is that you only need one!

ADR_REG: process ( CLK_I ) begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) A_O( 2)

Reply to
Marc Randolph

Thanks a lot for the comments Marc,

But my main question is that when I look at the RTL View of the vhdl file I see that uses a D flip-flops and feedbacks the outputs of these to the input of a mux that select with LOAD if the input to the Dflip-flops are the previous output (A_O) or the present input (V_I). I will use the Altera CPLD Max7000s that seems to have a D flip-flop with enable input and I would like that the LOAD input would go to the Enable input of the flip-flops instead of the feedback + mux solution and leaving unconnected the enable input of the flip-flop. How to do this?

Thanks a lot and best regards,

Javi

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Reply to
javid

Howdy Javi,

Unless there is a very severe bug in the synthesis tools that you are using, you do this by using one (and _only one_) "if rising_edge(clk)" statement per process. See below for examples.

Marc

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Reply to
Marc Randolph

Javi,

You haven't defined your FF completely. That's probably why you have a mux.

You should have done something like

process (clk, reset) begin if reset = '1' then data '0'); elsif clk'event and clk = '1' then if load = '1' then data(18 downto 2) Thanks a lot for the comments Marc,

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Reply to
Luc Braeckman

Hey Javid, Using Synplify? Look up syn_direct_enable in the manual. Cheers, Syms.

Reply to
Symon

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