Hello,
Started to look at the xapp635 to implement link port interface in Virtex II device. I ran a simulation (VHDL version) with the test bench that came with the app note and it did not pass the test. There is a bug in the receiver implementation. It fails at the very first reception.
I have identified the bug to be we_en signal going to the block ram.
Did anyone have any other issues with this core? The app note claims to have achieved 500 Mb/s per line, which translates to 250 MHz clock. Now I have my suspicions on these numbers :-). Does anyone have any numbers that they achieved?
The test board Xilinx used seems to be Danube DSP board from Bittware. The Bittware website claims a max throughput on these links to be 1GB/s which translates to 125 MHz clock rate.
Maybe someone had better luck with Verilog version of the core. Cursory look into verilog source files tells me it also has the same bug.
Fixing the bug is going to be a pain as there are no comments what so ever in the code. Looks like they intentionally stripped all the comments before releasing the code. Wondering if its better to write my own receiver based on the same technique rather than trying to fix this one.
Wondering if I can open a webcase or 'bug' Xilinx about this one as its only a xapp, is free and comes with no warranty what so ever.
Brijesh