I have a system generator model that utilizes the DDS v4.1 block. I wish to upgrade to the DDS v5.0 block to take advantage of some of the new features. However I have noticed that the interface has changed. My specific application utilizes the phase increment register and a constant phase offset of zero. In my v4.0 design, the accumulator width is set to 32 bits which configures the data input as a 32.32 unsigned integer. The output width is also configurable I use a 16-bit width, which gives a 16.15 signed output and a signal ranging between +/- 1 peak-to-peak. When I try using the v5.0 core with the Frequency set to programmable, it asks for a signed input at the data port. That seems odd because the value should always be positive. The width of this input seems to be set by the frequency resolution. Also I see nowhere where I can set the output resolution or amplitude and the signal is now between +/- 0.5 rather than +/- 1. How can I configure the new core to have the same interfaces as the old ones.? Thanks,
-Ira Thorpe