Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions:
1.- There is very little documentation. I've only found information at th Virtex-4 Libraries Guide for HDL Designs. But then again, it doesn't sa much about the protocol. Have anybody find more info, or successfull worked with it before? 2.- The manual says I can setup the I/O width to 8, but it doesn't seem t be working.I am using ISE 9.2 SP3
Any information will be appreciated.
alonzo
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