| The WISHBONE DATASHEET MUST indicate the port size. The port size | MUST be indicated as: 8-bit, 16-bit, 32-bit or 64-bit.
Does this mean I can't use dat_i for the update data? With Verilog and VHDL it is no problem to use 4 bit port sizes or even odd sizes, like 3 bits. Is there any other drawback if I use 4 bit dat_i, besides from not conforming to the Wishbone spec?