How do I perform RTL simulation with a Core Generator RAM and multiplier?

Hi, there:

How do I perform simulation with Core Generator module? Where can I find the definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0?

Best Regards, Kelvin

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Okie I got it...I found Core Gen manual...

Accidentally I generated DP-RAM in V5, but MULT in V6, will that hurt the simulation or synthesis? I use ISE 6.03i...

Kelvin

the

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